Dynamic and differential CMOS logic with signal-independent...

Details Dynamic and differential CMOS logic with signal-independent... Dynamic and differential CMOS logic with signal-independent...

2004-09-17

2008-08-26

Chang, Daniel D (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S122000, C326S113000

Reexamination Certificate

active

07417468

ABSTRACT:
A dynamic and differential CMOS logic style is disclosed in which a gate uses a fixed amount of energy per evaluation event. The gate switches its output at every event and loads a constant capacitance. The logic style is a Dynamic and Differential Logic (DDL) style. The DDL style logic typically has one charging event per clock cycle and the charging event does not depend on the input signals. The differential feature masks the in-put value because a precharged output nodes is discharged during the evaluation phase. The dynamic feature breaks the input sequence: the discharged node is charged during the subsequent precharge phase.

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Tiri et al., “A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards,” ESSCIRC 2002, Proceedings of the 28thEuropean Solid-State Circuit Conference, Sep. 24-26, 2002, Florence, Italy, 2002, pp. 403-406.
Huang et al., “New CMOS Differential Logic Circuits for True-Single-Phase Pipelined Systems,” Circuits and Systems, 1994, ISCAS 1994, 1994 IEEE International Symposium on London, UK May 30-Jun. 2, 1994, New York, NY, USA, vol. 4, May 30, 1994, pp. 15-18.

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