Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2007-02-06
2007-02-06
Rinehart, Mark H. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S317000, C710S305000, C710S307000
Reexamination Certificate
active
10904880
ABSTRACT:
Many Peripheral Component Interconnect Express (PCIE) lanes are available between a host and peripherals inserted into slots. Each PCIE lane is a bi-directional serial bus, with a transmit differential pair and a receive differential pair of data lines. The host has 2Nprimary lanes plus one extra lane. The extra lane is allocated to a slot when another slot uses all 2Nprimary lanes. The extra lane ensures that a low-priority peripheral has at least one lane when a high-priority peripheral requires all primary lanes. A partial cross-bar switching matrix between the host and peripheral slots switches lanes at the physical layer using transistor bus switches. A switch controller can be programmed by configuration software to enable transistor bus switches to allocate and connect host lanes to slot lanes. Peripherals can have 1, 2, 4, 8, 12, or 16 lanes allocated and may be inserted into any of the slots.
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Auvinen Stuart T.
gPatent LLC
Pericom Semiconductor Corp.
Phan Raymond N
Rinehart Mark H.
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