Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-08-21
2001-05-29
Le, Dieu-Minh T. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S200000, C710S220000
Reexamination Certificate
active
06240476
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to computer systems, and more specifically to a computer system in which bus master control lines can be dynamically allocated to connected peripheral devices.
2. Description of Related Art
The PCI (Peripheral Component Interconnect) bus is a standardized local bus that is used for communication between a CPU and its peripherals. The PCI bus allows for system board connection of high-speed peripherals and for connecting add-in cards to the system board. The PCI bus now dominates the desktop PC (personal computer) market as the primary way of connecting peripherals to the CPU, and variants of the standard PCI bus have evolved for industrial, compact, and mobile applications. The PCI bus and connected devices operate in accordance with the PCI specification, which is published by the PCI Special Interest Group. Because it is processor independent, any CPU or peripheral can be connected to the bus. In accordance with revision 2.1 of the specification, the PCI bus can provide a 32 or 64 bit data path that operates at a 33 or 66 MHz clock rate.
In a conventional PC, a system board houses a central processing unit CPU and its associated main memory, which is typically a large block of DRAM. A cache of faster SRAM memory, a logic control chip set, a CPU bus, and a PCI bus are also provided on the system board. Peripherals (such as a network interface controller, a graphics controller, and a sound controller) are connected to the PCI bus in the form of add-in cards. An ISA bridge may also be provided to allow ISA bus-based peripherals to be connected to the computer system. Additionally, the system board usually has ports for input and output devices such as a keyboard, a mouse, and a printer.
The PCI bus provides bus request lines and bus grant lines that allow devices connected to the bus to operate as bus masters. For a peripheral device to act as a bus master, the device must have bus master capabilities (i.e., the ability to request access to the PCI bus and then to generate the signals that are necessary to complete the data transfer in accordance with the PCI specification). Additionally, a unique bus request/grant line pair must be provided for the device so that bus requests can be generated independent of other bus activity.
While a large number of devices could theoretically be operated as bus masters, conventional logic control chip sets offer only a limited number of PCI bus request/grant line pairs. For example, the widely used logic chip sets manufactured by Intel Corporation (Santa Clara, Calif.) provide only four PCI bus request/grant line pairs. Furthermore, in conventional systems, the bus request/grant line pairs are hard wired to specific system board devices or add-in card slots. If a bus request/grant line pair is wired to a special system board device such as a universal serial bus (USB) controller, the number of add-in card slots available for bus master devices is reduced.
For example, the single board computer design guidelines (from the PCI Industrial Computers Manufacturing Group) allow up to four PCI bus master devices to be connected as add-in cards. However, devices on the computer board itself may also need to operates as bus masters. In such a conventional computer system, even when the on-board device is not needed in the present system configuration (e.g., if no peripheral devices are connected to the USB), the number of other devices that can operate as bus masters is limited. In other words, regardless of which devices are actually installed and being used in the system, the only way to change the allocation of the bus request/grant line pairs is to change the system board.
SUMMARY OF THE INVENTION
In view of these drawbacks, it is an object of the present invention to remove the above-mentioned drawbacks and to provide a computer system in which bus master control lines can be dynamically allocated to connected peripheral devices. The bus request/grant line pairs of the system control logic and the line pairs for physical devices are selectively coupled through an allocation control circuit. Based on a set of enable signals, the allocation control circuit allocates the bus request/grant line pairs to specific devices in the system. In this manner, the bus master control lines can be dynamically directed to the appropriate devices in accordance with the present configuration of the computer system.
According to one embodiment of the present invention, a computer system is provided that includes a system bus, peripheral devices, bus control logic having bus control lines for bus master operation, and an allocation control circuit. The allocation control circuit, which is connected to at least one of the bus control lines from the bus control logic and at least two of the peripheral devices, couples the connected bus control line to one of the connected peripheral devices so that the one connected peripheral device can operate as a bus master on the system bus. In a preferred embodiment, the allocation control circuit includes switches that are controlled by the system software.
Another embodiment of the present invention provides a method of allocating bus master control lines to peripheral devices connected to a bus. According to the method, the bus master control lines and the peripheral devices are connected to an allocation unit. It is determined which peripheral devices to connect to which bus master control lines, and the allocation unit is directed to couple each bus master control line to one of the peripheral devices so that the selected peripheral devices can operate as bus masters on the bus. In one preferred method, the determination of which peripheral devices to connect to which bus master control lines is performed based on user preferences and/or system-detected peripheral devices, and the system software controls the allocation unit by supplying enable signals that specify which bus master control lines to coupled to which peripheral devices.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.
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Garcia Ray
Honeycutt Kendall A.
Still Stephen E.
Bongini Stephen C.
Fleit Kain Gibbons Gutman & Bongini P.L.
International Business Machines - Corporation
Le Dieu-Minh T.
Vo Tim
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