Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2008-01-11
2011-10-11
Rojas, Midys (Department: 2185)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
Reexamination Certificate
active
08037278
ABSTRACT:
What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If the format control field is enabled, a frame address of a large block of data in main storage is obtained from the translation table entry. The large block of data is a block of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a desired block of data within the large block of data in main storage. The desired large block of data addressed by the translated address is then accessed.
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Greiner Dan F.
Heller Lisa C.
Osisek Damian L.
Pfeffer Erwin
Slegel Timothy J.
Campbell John E.
International Business Machines - Corporation
Rojas Midys
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