Dynamic access control of a function to a collective resource

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing

Reexamination Certificate

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C711S100000, C711S154000

Reexamination Certificate

active

06959371

ABSTRACT:
Access by a function to a collective resource is controlled by requiring that the function waits for a minimum number of clock cycles CLK called latency [LAT] between two successive accesses of the function. The function is further required to wait a number of cycles called penalty [PEN] which is higher than the latency between two successive accesses when a given number of successive accesses separated in time by at least the value of the latency has taken place beforehand. Registers [REG1, REG2] are decremented (or incremented) with each clock cycle and incremented (or decremented) with each access of the function to the collective resource. Tests [T1, T3, T4] are made with the contents of the registers to authorize [GRT] the access to the collective resource.

REFERENCES:
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patent: 6112019 (2000-08-01), Chamdani et al.
patent: 6266741 (2001-07-01), Hui et al.
patent: 6282614 (2001-08-01), Musoll
patent: 6324643 (2001-11-01), Krishnan et al.
patent: 0921468 (1999-06-01), None

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