Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-09-30
2004-12-07
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06829752
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application P2001-305706 filed on Oct. 1, 2001; the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an analysis system for a semiconductor integrated circuit and an analysis method of the same, which finds the duty of a transistor in a large-scale logic circuit using an analog circuit simulator and a logic circuit simulator.
2. Description of the Related Art
In the design stage of a semiconductor integrated circuit, there are many cases where the duty of a transistor—the element activation rate or the bias transition probability of the transistor—is required, with the duty of a transistor mainly being required when analyzing problems in reliability. Here, the duty of the transistor means the percentage which the transistor is at a certain predetermined bias status within a certain specified period of time. The specified bias status is arbitrarily defined in accordance with the details that are to be analyzed.
Conventionally, to find the duty of the transistor, there is a method whereby the duty of the transistor is obtained by performing a simulation using an analog circuit simulator such as that typified by HSPICE or the like, and then by analyzing the circuit dynamically. Although this method may be applicable for a circuit having approximately 40,000 to 50,000 transistors, its application is extremely difficult in large-scale logic circuits having 10 million gates per chip such as a System On Chip (SOC).
In addition, conventionally, a logic circuit simulator such as that typified by Verilog-XL or the like is used for logic circuit analysis. This simulator is able to analyze the logic functions of a large-scale logic circuit. Nevertheless, while the logic circuit simulator may be capable of finding the duty of each structural element configuring a logic circuit, for example a primitive cell such as a NAND gate or NOR gate, it is not capable of obtaining the duty of a transistor, for example, a MOS field effect transistor (MOSFET) configuring that primitive gate.
As described above, it is extremely difficult for a conventional analog circuit simulator to obtain the duty of a transistor in a large-scale logic circuit. Furthermore, a conventional logic circuit simulator is capable of analyzing a large-scale logic circuit, but cannot obtain the duty of a transistor. In other words, a problem lies in the fact that neither the analog circuit simulator nor the logic circuit simulator is capable of obtaining the duty of a transistor in a large-scale logic circuit.
SUMMARY OF THE INVENTION
An aspect of the present invention provides a system for analyzing a monolithic integrated circuit. The system includes: a) a logic circuit simulator configured to obtain the duty of a primitive cell that configures a logic circuit to be analyzed by performing a logic simulation of the logic circuit based on a netlist of the logic circuit and input vectors for the logic circuit; b) an analog circuit simulator configured to obtain the duty of a transistor that configures a primitive cell by performing an analog simulation of the primitive cell based on a netlist of the analog circuit of the primitive cell and input vectors for the primitive cell; and c) a synthesis module configured to obtain the duty of a transistor of the logic circuit by performing a synthesis of the duty of the primitive cell and the duty of the transistor.
Another aspect of the present invention provides a method for analyzing a monolithic integrated circuit. The method includes: a) obtaining the duty of a primitive cell, which configures a logic circuit to be analyzed, by performing a logic simulation of the logic circuit based on a netlist of the logic circuit and input vectors for the logic circuit; b) obtaining the duty of a transistor, which configures the primitive cell, by performing an analog simulation of the primitive cell based on a netlist of an analog circuit in the primitive cell and input vectors for the primitive cell; and c) obtaining the duty of a transistor of the logic circuit by performing a synthesis of the duty of the primitive cell and the duty of the transistor.
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Dinh Paul
Kabushiki Kaisha Toshiba
Siek Vuthe
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