Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-07-12
2004-12-07
Iqbal, Nadeem (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S012000
Reexamination Certificate
active
06829723
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a communication system, and more particularly, to duplicating processors and a method for controlling anomalous dual state of the duplicated processors.
2. Description of the Background Art
Generally, in order to improve reliability and stability in service of a communication system, a hardware path that transmits data is implemented by duplicating (active mode/standby mode), of which an active path is set at an initial stage through which data is transmitted, and if a disturbance occurs in the active path, a separately provided standby path is automatically switched to successively operated.
However, a communication system having the tightly coupled active/standby scheme that is physically constructed by hardware has disadvantages. The hardware architecture should be redesigned and a new operating system on it should be required. In addition, expense and time are required too much to develop a new programming language.
In an effort to overcome the drawbacks, as shown in
FIG. 1
, recent communication systems are established in that two processors
10
and
20
are loosely coupled through a network and heartbeat signals (HB_Tx/HB_Rx) that are periodically transmitted and received between the processors are used to process the duplication state by software.
For this purpose, the processors
10
and
20
respectively include blocks for performing the duplication function.
With reference to
FIG. 2
, the processor A
10
includes an incoming heartbeat processing block
11
, a duplication FSM (Finite State Machine) processing block
12
and an outgoing heartbeat processing block
13
. The processor B
20
has the same flow.
The incoming heartbeat processing block
11
receives a heartbeat (HB_Rx) from the processor B
20
, that is, the other processor (twin) and transfers state information of the twin
20
to the duplication FSM processing block
12
. If no heartbeat is received from the twin
20
within a predetermined time, it reports a network disturbance or a twin down to the duplication FSM processing block
12
.
The duplication FSM processing block
12
is charged with a corresponding state transition function according to the state information of the twin
20
included in the heartbeat (HB_Rx) or a switching event captured by the incoming heartbeat processing block
11
, so that it applies the state information of itself corresponding to each state to the outgoing heartbeat processing block
13
or renders the outgoing heartbeat processing block
13
to transmit a heartbeat signal immediately in every state transition.
The outgoing heartbeat processing block
13
transmits the heartbeat (HB_Tx) to the twin
20
immediately or periodically according to the state information applied from the duplication FSM processing block
12
.
FIG. 3
illustrates a state transition of the duplication FSM block in accordance with a conventional art.
The state transition process in accordance with the conventional art will now be described with reference to FIG.
3
.
Each state transition is made by a twin state event such as ‘Twin START’, ‘Twin ACTIVE’ or ‘Twin TIMEOUT’ or by an external event such as ‘Shutdown Command’, ‘Restart’ or ‘Manual Switchover’.
First, as the FSM is driven and all blocks on overall system are completely initialized, the duplication FSM allows the “INITIAL” state to transit to the “START” state.
And, the self processor confirms a state of the twin, and if the twin has been also started, the self processor is transited to ‘NEGOTIATION’ state to determine which side gives services as an active one. In the ‘NEGOTIATION’ state, it was predetermined that which of either one of two processors is to be active.
For example, if the processor A is set as an active processor, each processor confirms whether itself is the processor A in the ‘NEGOTIATION’ state. If either processor confirms itself as the processor A, it is transited to ‘ACTIVE’ state, or otherwise, it is transited to ‘STANDBY’ state.
Meanwhile, when the processor A is in ‘ACTIVE’ state, if the twin is in ‘ACTIVE’ state or if ‘Manual switchover’ occurs, the processor A is transited to ‘STANDBY’ state. And, if a network error or a disturbance occurs, the processor A is transited to ‘PENDING STANDBY’ state.
When the processor A is in ‘PENDING STANDBY’ state, it confirms a state of twin, and if the twin that is, the processor B is in ‘ACTIVE’ state, the processor A is transited to a ‘SYNCH’ state and then transited to ‘STANDBY’ state when synchronization is completed, while if the processor B is in ‘STANDBY’ state, the processor A is transited to ‘ACTIVE’ state.
Meanwhile, in case that the ‘Manual switchover’ occurs or the processor B is ‘Timeout’ before synchronization is completed, the processor A is transited to ‘ACTIVE’ state.
When the processor A is in ‘STANDBY’ state, if ‘Manual switchover’ occurs, the processor A is transited to ‘ACTIVE’ state. In case that the twin (processor B) is in ‘STANDBY’ state, the processor A is transited to ‘PENDING ACTIVE’ state and confirms a state of the twin. If the processor B is in ‘STANDBY’ state, the processor A is transited to ‘ACTIVE’ state, or otherwise, it is transited to ‘STANDBY’ state.
However, in case that the duplication is implemented by software through network as described above, there is a possibility that the network disturbance occurs or the network resources such as a cable or a hub are defected or disturbed. Then, each processor would judge that the twin has gone down, resulting in that both processors become active, which makes a confusion for external network elements/participants that mutually works with the processors, causing a problem failing to perform a normal operation.
In addition, even though the disturbance is restored, at just the time of restoration of the disturbance, it may fall to an anomalous dual state, though it happens at few random.
Moreover, if the two processors become all ‘ACTIVE’ state, since they recognize the other party as being in ‘ACTIVE’ state based on the received heartbeat, itself is accordingly transited to the ‘STANDBY’ state immediately. Meanwhile, in case that the two processors become all in ‘STANDBY’ state, since they recognize the other party as being in ‘STANDBY’ state based on the received heartbeat, itself is accordingly transited to the ‘PENDING ACTIVE’ state immediately. The difficulty is met in case that the twin may do the same action at the time.
If the twin is not the ‘PENDING ACTIVE’ nor ‘ACTIVE’, itself is transited to the ‘ACTIVE’ state. In this respect, normally, there is time differences to an extent in receiving the heartbeat, so that it may be prevented from falling into a double active state out of the ‘PENDING ACTIVE’ state.
That is, at this stage, differences are made in the receiving intervals of the heartbeat, so that the party that first reaches the ‘PENDING ACTIVE’ state is transited to an active state and the party that reaches later is transited to the ‘STANDBY’ state, thereby maintaining a normal state.
However, if the heartbeat is transmitted or received at the accurately same time, an anomalous dual active/standby state is inevitably caused. Then, a state fluctuation phenomenon may occur that transition is made to the dual active/standby state, failing to perform a normal duplication.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide duplicating processors and a method for controlling anomalous dual state in which seeds for generating random numbers are differently allocated when each processor is initialized to generate the different random number and transmission period of a heartbeat is continuously changed by using the random number, thereby avoiding an anomalous dual state.
Another object of the present invention is to provide a method for controlling duplicating processors which is capable of quickly restoring an anomalous dual state even though it occurs due to an abnormally on a network or on a system.
To achieve these and other advantages and in accordance with
Bonura Timothy M.
Fleshner & Kim LLP
Iqbal Nadeem
LG Information & Communications Ltd.
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