Duplicated double checking production rule set for...

Electronic digital logic circuitry – Reliability

Reexamination Certificate

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C326S010000, C326S014000, C326S093000

Reexamination Certificate

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11375390

ABSTRACT:
Systems and methods for mitigating the effects of soft errors in asynchronous digital circuits. Circuits are constructed using stages comprising doubled logic elements which are connected to c-elements that compare the output states of the double logic elements. The inputs of logic elements in a stage are inhibited from changing until the outputs of the c-elements of that stage are enabled. The c-elements inhibit the propagation of a soft error by halting the operation of the circuit until the temporary effects of the soft error pass.

REFERENCES:
patent: 7036059 (2006-04-01), Carmichael et al.
patent: 2005/0127971 (2005-06-01), Hoff

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