Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2005-10-17
2008-09-09
Chaudry, Mujtaba K (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S758000
Reexamination Certificate
active
07424664
ABSTRACT:
A duplicate detection circuit for a receiver includes a CRC generator for generating a CRC value of frame header information, and a control circuit coupled to the CRC generator. The control circuit has a first output, a second output, and a control input. When the control input is not set, the control circuit outputs the CRC value at the first output. When the control input is set, the control circuit outputs the CRC value at the second output. A buffer has an input coupled to the first output of the control circuit. A compare circuit has an input coupled to an output of the buffer and another input coupled to the second output of the control circuit. The compare circuit compares a CRC value at the second output of the control circuit with a CRC value stored in the buffer, and outputs a duplicate indication when detecting a match.
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patent: 6609226 (2003-08-01), Figueira
patent: 6665278 (2003-12-01), Grayson
patent: 7353446 (2008-04-01), Gorshe
patent: 2003/0081603 (2003-05-01), Rune
patent: 2003/0123389 (2003-07-01), Russell et al.
Chaudry Mujtaba K
Faraday Technology Corp.
Hsu Winston
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