Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-07-17
2003-07-15
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
Reexamination Certificate
active
06594778
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a switching system, and more particularly, a duplexing processor in a switching system and method thereof.
2. Background of the Related Art
In general, a switching system includes a plurality of processors, which are required to process data on a real time basis, and are managed by a duplexing channel to prevent an interruption in processing of data even when a malfunction occurs. A duplexing channel is generally formed through a back plane between two processor boards having the same construction. While one processor is operating in an active mode, the other processor is operating in a standby mode. When a disturbance occurs at the active mode processor, the standby mode processor is switched to an active mode to successively perform the data processing.
As the processor is switched oil duplexing, the memories of the two processors should be identical to each other in order for the CPU of the standby processor to successively perform its normal operation. For this purpose, when the CPU of the active processor performs a data writing operation on its memory, it performs a concurrent writing operation when the data is one to be concurrently written into the memory of the standby processor. Accordingly, the same data is written into the same address of the memory of the active processor and into the memory of the standby processor. In order to identify whether the concurrent writing was successfully performed, the CPU of the active processor periodically compares the two memories of the two processor, thereby maintaining a coherency of the memories of the active processor and the standby processor.
The operation of the background art duplexing processor will now be described with reference to FIG.
1
. The duplexing processor of the switching system consists of an active processor
10
and a standby processor
20
that are connected to each other through a duplexing bus. The active processor
10
and the standby processor
20
respectively include a CPU
11
and
21
, a memory
12
and
22
, a concurrent write logic unit
13
and
23
, and a standby read logic unit
14
and
24
.
The CPU
11
of the active processor
10
performs three kinds of operations: (1) a self-reading and writing operation for reading or writing only its own memory (active memory
12
); (2) a concurrent writing operation for concurrently writing the same data also on the memory (standby memory
22
) of the standby processor when writing the data on the active memory
12
; and (3) a standby reading operation for reading a data of a corresponding arbitrary address of the standby memory
22
to compare it with the data written in the arbitrary address of the active memory
12
to check whether the concurrent writing operation was correctly performed.
The three operations are divided by an agreement between a software and a hardware. For example, regarding ‘68000/68020/68030’ type CPUs in the line of 68XXX processors, the three operations are performed according to classification of an address field value, and a logic of the hardware is driven according to the address field value. While the three operations are performed by a UPA
0
/UPA
1
(UPA: User Page Attributes) of the CPU with respect to ‘68040/68060’.
For example, on the assumption of 128 Mbyte memory, the operation of the CPU are as shown Table 1 as follows:
TABLE 1
68000/68020/68030
68040/68060
address field)
(UPA bit)
(1) Self-reading and
0x00000000~0x07FFFFFF
UPA1:UPA0 = ‘00’
writing
(2) Concurrent writing
0xC0000000~0xC7FFFFFF
UPA1:UPA0 = ‘01’
(3) Standby reading
0x40000000~0x47FFFFFF
UPA1:UPA0 = ‘10’
(4) Reserved
Undefined
UPA1:UPA0 = ‘11’
In this manner, when the operation state of the CPU
11
is represented according to the setting of the address field value or the UPA bit value previously determined on the basis of software, the hardware drives logic that is suitable for the operation.
When an address field value or a UPA bit value corresponding to the ‘(2) concurrent writing’ operation of Table
1
is applied from the CPU
11
, the concurrent write logic unit
13
accesses the memory
22
of the standby processor through the duplexing bus and writes the same data into the two memories
12
and
22
. When an address field value or a UPA bit value corresponding to the ‘(3) standby reading’ operation of Table 1 is applied from the CPU
11
, the standby read logic unit
14
accesses the memory
22
of the standby processor through the duplexing bus and reads the data of the memory
22
to transfer it to the CPU
11
. The three operations of the background art duplexing processor will now be described.
1. Self Reading and Writing Operation
This operation is performed when the data written in the active memory
12
is desired to be read by the CPU
11
, and when the data is desired to be written only in the active memory
12
. That is, the data written into the memory
12
is not written into the standby memory
22
because the data wouldn't affect the operation of the CPU
22
.
First, the CPU
11
sets an address field value or a UPA bit value corresponding to the ‘(1) Self reading and writing’ operation of Table 1 and selects an address desired to be read or written. The units
13
and
14
corresponding to the duplexing logic are not driven, and only the corresponding active memory
12
is accessed. Thus, the data of the corresponding address is read or written.
2. Concurrent Writing Operation
This operation is performed when the data is desired to be concurrently written into the active memory
12
and the standby memory
22
by the CPU
11
. First, the CPU
11
sets an address field value or a UPA bit value corresponding to the ‘(2) concurrent writing’ operation of Table 1 and outputs a data to be written and its address. Thereafter, the data is written into the corresponding address of the active memory
12
, and simultaneously, the concurrent write logic unit
13
is driven.
The concurrent write drive unit
13
accesses the memory
22
of the standby processor and transfers the same data as the data transferred to the active memory
12
through the duplexing bus. Accordingly, the same data as that written in the active memory
12
is written into the corresponding address of the standby memory
22
.
3. Memory Coherency Maintaining Operation
This operation is performed to periodically identify whether the same data was written in the active memory
12
and in the standby memory
22
by means of the CPU
11
of the active processor
10
. Memory coherency enables the CPU
21
of the standby processor
20
to be able to continuously perform the operation of the previous active processor in case of the duplexing switch.
First, the active memory
12
is accessed and a data written in the corresponding address of the memory
12
is applied to the CPU
11
. Thereafter, when the CPU
11
selects the address field value or the UPA bit value corresponding to the ‘(3) standby read’ operation of Table 1 and the same address as above, the standby read logic unit
14
is driven.
The standby read logic unit
14
accesses the memory
22
of the standby processor, reads a data of a corresponding address of the memory
22
and transfers it to the CPU
11
through the duplexing bus. Thereafter, the CPU
11
compares the data as read from the active memory
12
and the data as read from the standby memory
22
. If the two data are identical, the CPU
11
repeatedly performs the above process to thereby compare the data of the next address.
Meanwhile, upon such comparison, if the two data of the memories
12
and
22
are not identical, the CPU
11
sets a field value of the discordant address or a UPA bit value corresponding to the ‘(2) concurrent writting’ operation of Table 1. Accordingly, the concurrent write logic unit
13
is driven so as to transfer a data of a predetermined address of the active memory
12
to the standby memory
22
through the duplexing bus. In this manner, the same data as the data written in the active memory
12
Abraham Esaw
De'cady Albert
Fleshner & Kim LLP
LG Information & Communications Ltd.
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