Duo-mode keeper circuit

Details Duo-mode keeper circuit Duo-mode keeper circuit

2005-05-03

2005-05-03

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S098000, C326S121000

Reexamination Certificate

active

06888377

ABSTRACT:
LSDL logic is provided with circuitry that has logic controls to provide two modes of operation. The half latch and the PFET that normally forms the keeper function on the dynamic node are modified. The inverter function of the series connected PFET and NFET have their corresponding positive and negative power supply terminals coupled to logic gates. In this way, the inverter may be turned ON so that the half latch functions as a keeper or it may be turned OFF to remove it from operating at all in the mode where the LSDL logic circuit needs to operate with a fast pulse clock. Likewise, the positive supply voltage may be removed while allowing the NFET device to operate to turn ON the PFET pull-up device for burn-in operation.

REFERENCES:
patent: 5543731 (1996-08-01), Sigal et al.
patent: 5831990 (1998-11-01), Queen et al.
patent: 5852373 (1998-12-01), Chu et al.
patent: 6404236 (2002-06-01), Bernstein et al.
patent: 6496038 (2002-12-01), Sprague et al.
patent: 6690204 (2004-02-01), Belluomini et al.
patent: 20040051560 (2004-03-01), Belluomini et al.

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