Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2001-10-18
2004-03-30
Nguyen, Van Thu (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S194000, C365S233100
Reexamination Certificate
active
06714472
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to semiconductor memory devices, such as Static Random Access Memory (SRAM) devices. More specifically, the invention relates to dummy wordlines that control the timing of the firing of sense amplifiers in memory devices in relation to the firing of wordlines in the memory devices.
2. State of the Art
As shown in
FIG. 1
, a conventional SRAM (not shown in its entirety) includes wordline selection and driving circuitry
10
that initiates the process of reading a logic bit from an SRAM cell
12
when a timing control
14
causes the circuitry
10
to activate a wordline
16
, thereby activating the SRAM cell
12
. The activated SRAM cell
12
dumps its logic bit onto bitlines
18
and
20
by inducing a voltage differential between the bitlines
18
and
20
representative of the logic bit. The timing control
14
then causes a sense amplifier (not shown) in column selection and sensing circuitry
22
to sense and amplify the voltage differential between the bitlines
18
and
20
. The amplified voltage differential, still representative of the logic bit output from the SRAM cell
12
, is then output through output buffers (not shown) for use by external circuitry (not shown).
The timing of the “firing” (i.e., the activation) of the sense amplifier in the column selection and sensing circuitry
22
in relation to the firing of the wordline
16
is important. When the sense amplifier is fired too early, the activated SRAM cell
12
may not have sufficient time to induce a voltage differential on the bitlines
18
and
20
that can be sensed by the sense amplifier. As a result, the sense amplifier may incorrectly sense a logic “0” bit, for example, on the bitlines
18
and
20
while the SRAM cell
12
is in the process of dumping a logic “1” bit onto the bitlines
18
and
20
. When the sense amplifier is fired too late, the SRAM cell
12
is no longer activated, so, again, the sense amplifier may sense the wrong logic bit on the bitlines
18
and
20
. Even when the sense amplifier is fired in a “window” of time between “too early” and “too late,” if the sense amplifier is fired toward the end of this window, time and power are wasted keeping the wordline
16
and the SRAM cell
12
activated until the end of the window. Thus, the sense amplifier is preferably fired in the beginning or the middle of the window of time between too early and too late in order to increase the speed with which logic bits are read from the SRAM cell
12
and to limit power usage.
Unfortunately, the timing control
14
does not always provide this preferred timing, because process variations during fabrication can vary the impedance-induced signal propagation delay along the wordline
16
, and thus the timing of the activation of the SRAM cell
12
, in a way that cannot be anticipated by the timing control
14
. As a result, the timing control
14
is typically designed with extra delay time between the firing of the wordline
16
and the firing of the sense amplifier in the column selection and sensing circuitry
22
to correct for those wordline signal propagation delays that fall within a typical range. Although this approach creates a working part, it does not enhance the speed of the part or reduce its power usage, as is desired.
The timing problem described above also arises in Dynamic Random Access Memory (DRAM) devices, and it has been addressed in a DRAM device
24
shown in
FIG. 2
manufactured by the Assignee of the present invention, Micron Technology, Inc. of Boise, Idaho. In the DRAM device
24
, the timing of the firing of column selection and sensing circuitry
26
in relation to the firing of wordlines (not shown) in an array
28
of DRAM memory cells (not shown) by wordline selection and driving circuitry
30
is controlled by a folded delay line
32
fabricated in the periphery
34
of the DRAM device
24
. The length of the delay line
32
is selected so a timing signal output by the circuitry
30
at the same time a wordline in the array
28
is fired propagates along the delay line
32
and arrives at the circuitry
26
in time to fire the circuitry
26
at the preferred time described above.
Again, process variations during fabrication vary the impedance-induced signal propagation delay of the folded delay line
32
, and of the wordlines in the array
28
, in such a way that the delay line
32
must include extra delay length to accommodate variations in the propagation delays that fall within a typical range, in much the same way that the timing control
14
of
FIG. 1
must include extra delay time. As a result, the delay line
32
is not a reliable means of achieving the preferred timing described above, and thus does not reliably meet the goals of increased speed and reduced power usage.
Therefore, there is a need in the art for an improved device and method for controlling the timing of the firing of sense amplifiers and other column selection and sensing circuitry in memory devices, such as SRAMs and DRAMs, in relation to the firing of wordlines in such memory devices. Such an improved device and method should accommodate normal process variations that vary signal propagation delays in such memory devices while increasing speed and limiting power usage.
SUMMARY OF THE INVENTION
An apparatus in accordance with the present invention controls the timing of the firing of column selection and sensing circuitry, such as sense amplifiers, in a semiconductor memory, such as a Static Random Access Memory (SRAM) or a Dynamic Random Access Memory (DRAM). The apparatus includes a dummy wordline fabricated within an array of memory cells in the semiconductor memory. The dummy wordline has a length selected so the dummy wordline can delay a timing signal traversing its length by a selected amount of time before the timing signal fires the column selection and sensing circuitry.
By selecting a suitable length for the dummy wordline, the timing of the firing of the column selection and sensing circuitry can be controlled. Also, the dummy wordline preferably receives the timing signal from wordline driving circuitry at the same time the wordline driving circuitry fires an active wordline in the array of memory cells so the apparatus of the present invention controls the timing of the firing of the column selection and sensing circuitry in relation to the firing of active wordlines in the semiconductor memory.
Because the dummy wordline is fabricated within the array of memory cells, fabrication process variations alter the impedance characteristics of the dummy wordline in relatively the same way as they alter the impedance characteristics of active wordlines in the array. As a result, the time delay associated with the active wordlines varies in the same manner as the time delay associated with the dummy wordline, so no delay time need be built into the dummy wordline to accommodate variations in the time delay associated with the active wordlines. As a result, the length of the dummy wordline can be selected to optimize the timing of the firing of the column selection and sensing circuitry so it occurs at a preferred point in a window of time between too early and too late, thus reducing power usage by minimizing the active time of wordlines and increasing the speed of the semiconductor memory by optimizing the timing of its column selection and sensing circuitry.
In other embodiments of the present invention, a semiconductor memory, an electronic system, and a semiconductor wafer include the inventive dummy wordline described above.
In an inventive method of the present invention, the timing of the firing of column selection and sensing circuitry in a semiconductor memory is controlled by first generating a timing signal for firing the circuitry. Arrival of the timing signal at the column selection and sensing circuitry is then delayed by impeding conduction of the signal to the circuitry with impedance characteristics that are substantially the same as impedance characteristics of an active word
Micro)n Technology, Inc.
Nguyen Van Thu
TraskBritt
LandOfFree
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