Dummy wordline circuitry

Details Dummy wordline circuitry Dummy wordline circuitry

1999-04-29

2001-06-26

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

Reexamination Certificate

active

06252814

ABSTRACT:

TECHNICAL FIELD
The present invention relates in general to memory cells for use in storage systems and information handling systems, and more particularly, to a memory cell having dummy wordline circuitry.
BACKGROUND INFORMATION
One of the goals in designing microelectronics circuitry, especially circuitry pertaining to the retrieval and storage of information in memory cells, is an increase in the speed of memory accesses. Often, the performance of a data processing system is mostly dependent upon the speed of memory accesses, because microprocessor frequencies are far more advanced.
Such memory systems often use static random access memories (“SRAM”). Dual rail SRAM cells are well-known in the prior art.
FIG. 7
illustrates a prior art SRAM cell
700
having a standard design. Each SRAM cell
700
requires a bitline
713
and its complement
712
. Cell
700
operates differentially between bitline
713
and complement
712
. Precharge transistor
720
precharges bitline
713
, and precharge transistor
708
precharges complement bitline
712
. Control transistor
716
gates data from complement line
712
to the latch formed of cross-coupled inverter
724
and
726
. Transistor
716
and
730
are coupled to dual rail wordlines. Transistor
714
is a write enable control transistor. Transistor
710
is a write enable control for complement bitline
712
. The outputs of cells
700
are connected to a sense amplifier (not shown) for transmission of the data at standard levels out of the storage array (not shown) for use by the information handling system.
Conventional tag and cache memory arrays usually have only one dummy wordline to track the duration of the wordline turning on during a read operation. This dummy wordline can also be used to disable the wordline after enough differential voltage has developed at the sense nodes. At the same time, the dummy wordline may be used to generate the isolation signal to isolate the bitlines from the sense node, and to enable the sense amplifier signal for sensing. All of the above takes place during a read cycle.
Dummy wordlines are utilized, because they track the timing through the memory array better than a plurality of invertors used to simulate the delay of the wordline signal through the memory array.
A typical access to such tag and cache arrays involves a read/reload-swap cycle, whereby data is read from the memory cells during a read cycle and then replaced during the reload-swap portion of the cycle, which is essentially a write operation. The write/reload-swap takes place in the second half of the cycle after the read portion, and a wordline is needed to fire off again when the write clock arrives. To enable the wordline again in the second half of the cycle, the dummy wordline would be needed to precharge again after it disables the wordline in the read cycle. This precharged action, in turn, will precharge the isolation and sense amp signals. In the write cycle, or reload-swap, the isolation signal continues to be active to disconnect the bitlines and the sense node so that no write through occurs. This implies that the isolation and sense amp circuits need to be dynamic and therefore the logic and timing would be more complicated and could potentially cause the memory array to run slower. As a result, there is a need in the art for an additional dummy wordline circuit to fire off during the write/reload-swap operation and reset the tag or cache array to an initial state for the next read operation.
Essentially, with one dummy wordline, at a high frequency operation, there is insufficient time to precharge the single dummy wordline for the next cycle. With such read/write processes occurring in the same cycle, the prior art has alternatively tried to keep the single wordline at an asserted state, but this consumes too much power.
Therefore, there is a need in the art for a dummy wordline circuit that can operate at higher frequencies.
SUMMARY OF THE INVENTION
The present invention addresses the foregoing need by implementing two dummy wordlines within a memory array. One of the dummy wordlines is used for the read portion of the access cycle, while the second dummy wordline is used for the write portion of the access cycle.
At the beginning of the read/swap cycle, all wordlines, bitlines, dummy wordlines, and dummy bitlines are precharged to appropriate voltages. At the rising edge of the beginning of the read cycle, a wordline enable signal is activated to enable the read dummy wordline and the wordline. A time delay later, the read dummy wordline signal discharges the dummy bitline read signal, which then disables the wordlines, and the read dummy bitline triggers the isolation and sense amp signals.
In the second half of the read/swap cycle, the write signal is active (clock signal is negated). This causes the write enable signal to again become active. When the wordline enable signal is active, it activates the second dummy wordline write signal which in turn pulls down the write dummy bitline signal.
When the write dummy bitline signal goes active (low), it pulls the write enable signal down to terminate the write (since the write process is completed by that time). It also enables a bitline equalization signal again to precharge the bitlines for the next read cycle. It additionally triggers the isolation signal to allow the bitlines connecting to the sense amp for precharging of the sense nodes. It further kills the sense amp signals and kills the wordline enable and precharges all the wordlines again to a low state.
One advantage of the present invention is that it provides for better wordline tracking to ensure the write portion of the cycle is completed before the wordline is turned off. Another advantage of the present invention is that it improves the maximum operating frequency of the memory array. Yet another advantage of the present invention is that the memory array can operate in an asynchronous mode for the write portion of the cycle, meaning that the write can take place as soon as the read finishes without waiting for the falling edge of the clock. And yet still another advantage of the present invention is that all the logic for generating isolation and sensing signals does not have to be dynamic, therefore it can eliminate a lot of the problems associated with timing for dynamic circuitry.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.


REFERENCES:
patent: 4622655 (1986-11-01), Suzuki
patent: 4907200 (1990-03-01), Ikawa et al.
patent: 5062079 (1991-10-01), Tsuchida et al.
patent: 5485427 (1996-01-01), Ogawa
patent: 5596543 (1997-01-01), Sakui et al.
patent: 5657269 (1997-08-01), Nanamiya
patent: 5724294 (1998-03-01), Khieu

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