Dummy word line driving circuit for a MOS dynamic RAM

Details Dummy word line driving circuit for a MOS dynamic RAM Dummy word line driving circuit for a MOS dynamic RAM

1986-06-20

1988-07-12

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Differential sensing

365203, G11C 702

Patent

active

047574763

ABSTRACT:
A dummy word line driving circuit for a MOS dynamic RAM comprises a dummy word line controller connected to each end of a pair of dummy word lines. A sub-decode signal which is opposite to the one inputted to a dummy word driver and a dummy set signal for writing a bit line information into a not-selected dummy cell are inputted to the dummy word line controller. Means for applying a dummy equalizing signal is connected to two full-sized dummy cells, for equalizing the two before the dummy word line is driven. The two full-sized dummy cells are equalized by the signal, resulting in a charge amount, which is to be a reference value, of a half of a full-sized memory cell.

REFERENCES:
patent: 4122546 (1978-10-01), von Basse et al.
patent: 4504929 (1985-03-01), Takemae et al.
patent: 4547868 (1985-10-01), Childers et al.
IEEE Journal of Solid-State Circuits, vol. SC-15, No. 5, Oct. 1980, pp. 839-846, J. Y. Chan et al., "A 100 ns 5 V Only 64K.times.1 MOS Dynamic RAM".

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