Dummy fill patterns to improve interconnect planarity

Details Dummy fill patterns to improve interconnect planarity Dummy fill patterns to improve interconnect planarity

1997-02-24

1998-12-29

Everhart, Caridad

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438631, 438646, 438926, 438697, H01L 21463

Patent

active

058541250

ABSTRACT:
A method of improving the planarity of spin-on glass layers in semiconductor wafer processing is disclosed. Gaps in between active conductive traces on a trace layer of a semiconductor wafer that exceed a predetermined threshold distance are provided with dummy surfaces arranged in a micro-pattern in order to improve the planarity achieved in subsequently applied spin-on glass layers. In some embodiments, the predetermined threshold distance is greater than approximately 2 micrometers, as for example in the range of approximately 4.65 to 5 micrometers. In some applications, both the active conductive traces and the dummy surfaces are formed from a metallic material that is deposited in one single step with a dielectric layer being deposited over both the active conductive traces and the dummy surfaces prior to application of the spin-on glass layer.

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