Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
Reexamination Certificate
2001-04-09
2004-08-03
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error count or rate
C714S703000
Reexamination Certificate
active
06772378
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a dummy error addition circuit, and more specifically, to a dummy error addition circuit that can generate, in simulation mode, a bit error that occurs in a transmission path so as to be used for a performance check of a decoder to decode an orthogonal modulation signal.
BACKGROUND ART
As a hierarchy transmission system that transmits a combination of a plurality of transmission systems with different reception C/N's in digital broadcasting, for example, a hierarchy transmission system using m-phase phase shift keying (PSK) modulation time multiplexing is known. This system allows stable digital signal transmission, but in the case where C/N deteriorates in a transmission path, this system cannot help being affected by noise due to bit errors.
For this reason, in order to test the performance of a decoder in a digital broadcasting receiver, there is a demand for a dummy error addition circuit, which generates, in simulation mode, a bit error that occurs in a transmission path, supplies orthogonal modulation symbol data with the dummy error being added to the decoder to test whether or not the decoder has a sufficient characteristic such as the error correction ability. However, there has never been such a dummy error addition circuit so far.
It is an object of the present invention to provide a dummy error addition circuit to add a dummy error to various orthogonal modulation symbol data such as PSK modulation symbol data and QAM modulation symbol data.
DISCLOSURE OF THE INVENTION
The dummy error addition circuit of the present invention adds a bit data error to orthogonal modulation symbol data, and according to the dummy error addition circuit of the present invention, a bit error is added to the orthogonal modulation symbol data, and therefore it is possible to check the performance of a decoder by supplying the orthogonal modulation symbol data with the dummy error added to the decoder.
The dummy error addition circuit of the present invention is provided with error pulse generating means for randomly generating error pulses at a rate based on a specified bit error rate and characterized by adding a bit error based on the error pulses. Therefore, according to the dummy error addition circuit of the present invention, error pulses are generated randomly at a rate based on a specified bit error rate and a bit error is added to the orthogonal modulation symbol data based on these error pulses, which makes it possible to simulate a bit error in a transmission path.
Furthermore, the dummy error addition circuit of the present invention is provided with bit selecting means for randomly selecting a bit to which to add an error from one bit in the orthogonal modulation symbol data and the bit position in the orthogonal modulation symbol data to which the error is added is selected randomly, and therefore it is possible to simulate bit errors in various transmission paths.
The dummy error addition circuit of the present invention is basically provided with counter means for periodically generating a series of monotonously increasing or decreasing numerical values, random signal generating means for generating a series of random number values, generating means for generating an error occurrence indication signal when the output values of the counter means and the random signal generating means for generating a series of random number values match as a result of a comparison and adding means for adding a bit error to a specific symbol data in an orthogonal symbol data series when the error occurrence indication signal is generated in response to the error occurrence indication signal, the orthogonal symbol data series and the error occurrence indication signal. Then, the random number values output from the random signal generating means are updated in the cycle of the series of numerical values output from the counter means, and the dummy error addition circuit of the present invention is also provided with means for selecting a bit to add an error from the bits in specific symbol data when the error occurrence indication signal is generated in response to the error occurrence indication signal, the random number value series and orthogonal modulation symbol data series and adding an error to this bit. This allows symbol data to add an error to be selected randomly in an average cycle (based on a bit error rate specified beforehand) from a predetermined orthogonal modulation symbol data series and allows the error to be added to a bit at a specific bit position randomly selected in the symbol data.
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Horii Akihiro
Ishihara Kenichi
Shinjo Soichi
Shiraishi Kenichi
Kabushiki Kaisha Kenwood
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Tu Christine T.
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