Dummy cell structure for MIS dynamic memories

Details Dummy cell structure for MIS dynamic memories Dummy cell structure for MIS dynamic memories

1979-10-11

1981-04-28

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Differential sensing

3072385, 365174, G11C 1140

Patent

active

042649650

ABSTRACT:
A structure of a dummy cell of a one-transistor cell type dynamic RAM made up of MISFETs formed in the shape of an integrated circuit within a single semiconductor substrate, the dummy cell structure comprising a pair of first gate electrode layers which is made of a first polycrystalline silicon layer, a second gate electrode layer which is made of a second polycrystalline silicon layer formed on the semiconductor substrate between the pair of first gate electrode layers through a gate insulating film, means for applying a fixed bias voltage to the second gate electrode layer in order to operate it as a capacitor, means for applying a clear control signal to one of the pair of first gate electrode layers in order to operate it as a clearing MISFET, and means for applying a word select signal to the other first gate electrode layer in order to operate it as a transfer MISFET.

REFERENCES:
patent: 4195357 (1980-03-01), Kuo et al.

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