Dummy cell arrangement for an MOS memory

Details Dummy cell arrangement for an MOS memory Dummy cell arrangement for an MOS memory

1980-10-06

1982-12-07

Stellar, George G.

Static information storage and retrieval

Read/write circuit

Differential sensing

365205, G11C 700

Patent

active

043631118

ABSTRACT:
A dummy cell arrangement is described for sensing the logic state of an accessed memory cell in an MOS memory in which a memory cell capacitor of a given size is associated with each memory cell. In the preferred embodiment, a plurality of dummy cells are included, each of which has a dummy capacitor of substantially the same given size as a memory cell capacitor. When the state of an accessed memory cell is to be sensed, its memory cell capacitor is coupled to a bit line to change the voltage thereon and a selected dummy cell capacitor is coupled to a pair of bit lines so as to effect substantially equal transfers of charge between the dummy capacitor and the bit lines to which it is coupled. The resulting voltage on the memory cell capacitor's bit line is compared to the voltage on one of the dummy capacitor's bit lines so as to determine the logic state of the accessed memory cell.

REFERENCES:
patent: 3760381 (1973-09-01), Yao

Affiliated with

Also associated with

Rating

Dummy cell arrangement for an MOS memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dummy cell arrangement for an MOS memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dummy cell arrangement for an MOS memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1906840