Duel die package

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S666000, C257S686000, C257S692000, C257S696000

Reexamination Certificate

active

06864566

ABSTRACT:
An improved dual die package is disclosed. The dual die package includes a first lead frame connected to a first semiconductor chip and a second lead frame connected to a second semiconductor chip. The first leads and the second leads are electrically connected to one another using a wirebonding process rather than a thermocompression process thereby allowing conventional packaging equipment to be used when manufacturing a dual die package.

REFERENCES:
patent: 5303120 (1994-04-01), Michii et al.
patent: 5804874 (1998-09-01), An et al.
patent: 6252299 (2001-06-01), Masuda et al.
patent: 6407333 (2002-06-01), Schroen
patent: 04-320365 (1992-11-01), None
patent: 05-067726 (1993-03-01), None
patent: 05-291486 (1993-11-01), None
patent: 08-316403 (1996-11-01), None
patent: 1019980034119 (1998-08-01), None
patent: 1019990085220 (1999-12-01), None
patent: 102000035276 (2000-06-01), None
patent: 1020000050487 (2000-08-01), None

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Duel die package does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Duel die package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Duel die package will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3367564

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.