Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-30
2003-11-04
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S288000, C257S296000, C257S368000, C257S387000
Reexamination Certificate
active
06642584
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to semiconductor structures and methods of fabrication thereof, and more particularly, to the integration of embedded memory, such as an embedded DRAM, in a logic process lacking borderless contacts. In accordance with this invention, a semiconductor structure and method of fabrication are presented wherein a type of borderless contact is improvised in an array cell in order that contacts can land over gate electrodes without effecting a dual work function logic process, thereby allowing for improved array density.
BACKGROUND OF THE INVENTION
The integration of logic arrays and memory arrays, such as dynamic random access memory (DRAM), within a single semiconductor structure continues to increase every year. This integration of logic and DRAMs to achieve dense high performance embedded dynamic random access memory (EDRAM) technology presents two basic tradeoffs: either a dense memory cell array with slower logic can be achieved, or an inefficient, larger memory cell array with faster logic is possible.
In the dense memory array with slower logic design, referred in the industry as merged DRAM logic (MDL), a high speed dual work function (DWF) logic support design is traded for a conventional DRAM (CDRAM) based single work function (SWF) design. A SWF design comprises relatively “slower” logic with a capped gate electrode leading to a very dense memory array design employing a borderless pitch array, i.e., an array that is borderless between the gate (word-line) and bit-line contact. The MDL design typically has a logic core performance that is 20-30% slower than the alternative large cell memory array and fast logic approach.
In the large cell memory array and fast logic approach, referred to in the industry as merged logic DRAM (MLD), a densely packed memory array cell is traded for the high speed dual work function (DWF) logic. A borderless array bit-line contact is given up, and the array cell efficiency is decreased by at least 30% compared with the above-described dense array and slower logic implementation (i.e., MDL design).
In view of the above tradeoffs, there exists a need in the art for a structure which integrates dual work function logic technology with a borderless contact to achieve MLD performance and MDL array efficiency, and which results in a cost effective, high performance embedded DRAM structure and process.
SUMMARY OF THE INVENTION
Briefly summarized, the present invention comprises in one aspect a semiconductor structure including a field effect transistor (FET) with a substantially cap-free gate and a conductive contact to a diffusion adjacent to the gate, wherein the conductive contact is borderless to the gate. The substantially cap-free gate is an MLD technology characteristic, while the borderless contact is a characteristic of the MDL design. In the array, this contact is typically used to connect to the memory bit-line. Note, that the contact may also be used in the logic core.
In a further aspect, a semiconductor structure is provided which includes a first material and a second material. The first material has a first contact hole with a horizontal surface of the first material being adjacent to the first contact hole. The second material extends over the first material and the second material comprises a second contact hole, with the second contact hole extending over the first contact hole to expose a portion of the horizontal surface. A conductor is disposed within the first contact hole, and a spacer lines the second contact hole and extends over the conductor. The spacer has a dimension sufficient so that no horizontal surface of the first material is exposed through the second contact hole.
In a further aspect, a method of processing a semiconductor is provided which includes: providing a substrate; forming a film on the substrate, the film having a top surface; forming a hole through the film; providing an insulating layer having an opening aligned to the hole and larger than the hole so a portion of the top surface of the film is exposed; providing a material in the hole; and providing a spacer along sidewalls of the opening to shrink the opening and cover exposed portions of the top surface of the film, wherein the spacer may extend partially over the material within the hole.
Advantageously, this invention presents a semiconductor structure and method of fabrication wherein a borderless contact is provided within a dual work function logic process. Essentially, this invention employs the best elements of single work function logic and dual work function logic, and develops an MLD technology with exemplary features of MLD (i.e., DWF), and MDL (i.e., borderless contact). In accordance with the present invention, there is no need for a process fabricator to employ two tool sets for an integrated DRAM and logic design (as previously needed). The process embodiments presented leave the option open for silicide or non-silicide designs. The silicide process is easily integrated into the core logic process. In accordance with the present invention, each transistor gate is electrically isolated from the adjacent diffusion contact.
Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention.
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Li Yu-jun
Tonti William R.
Ye Qiuyi
Heslin Rothenberg Farley & & Mesiti P.C.
Jackson Jerome
Radigan, Esq. Kevin P.
Sabo, Esq. William D.
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