Dual work function gate conductors with self-aligned...

Details Dual work function gate conductors with self-aligned... Dual work function gate conductors with self-aligned...

1999-06-04

2001-08-14

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Diffusing a dopant

C438S301000

Reexamination Certificate

active

06274467

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of manufacturing integrated circuit chips, and more particularly to dual work function semiconductor devices and a method for producing these devices.
BACKGROUND OF THE INVENTION
Dual work function devices are becoming increasingly common in CMOS devices to provide enhanced PMOS performance. A transistor consists of a gate, a source, and a drain. In dual work function devices commonly practiced in the art, if the source and drain are doped N+, the polysilicon gate must also be doped n-type. Conversely, if the source and drain are doped P+, the polysilicon gate is doped p-type.
There are several problems which arise when forming a dual work function device. When the polysilicon gate is doped n-type or p-type, the dopant tends to penetrate the gate dielectric and enter the substrate. This limits the processing conditions used to form the device, the choice of a DRAM transfer device, as well as the materials that may be used as the gate dielectric. There are also numerous alignment problems which occur due to the additional implantation of dopants and a corresponding increase in throughput time. Several methods have been proposed for forming dual work function logic devices. However, with the ever increasing circuit densities in ULSI, it is becoming necessary to integrate high performance logic with high density DRAM. Unfortunately, the present technology for forming the gate conductors for high performance logic and high density DRAM is quite different.
FIG. 1
shows a prior art method which separately forms the PFET and the NFET in a dual work function logic device. The source/drain regions
2
,
3
and gates
4
,
5
are all doped at the same time. The gates are formed on the wells. As shown in
FIG. 1
, a photoresist
6
is formed over the p-well
7
and the NFET. A P+ dopant is then implanted in the n-well
8
to form the source/drain regions
2
as well to dope the polysilicon gate
4
P+. The NFET is formed in a similar manner implanting an n-type dopant with photo resist over the PFET.
U.S. Pat. No. 5,770,490 to Frenette et al. describes another method of forming a dual work function logic device. In this method, a first layer of doped material is formed over the entire substrate. The first layer is then removed in selected areas where doping opposite of the first layer is desired and a second layer of an oppositely doped material is formed over the entire surface. Drive in anneal is then performed to diffuse the dopants into the adjacent areas.
U.S. Pat. No. 5,605,861 to Appel proposes a similar solution for forming a dual work function logic device. Here, a layer of glass having a P+ dopant therein is formed over the substrate. This layer is then removed above the p-well and the polysilicon gate layer in this region is then doped n-type. The structure is heated to cause the P+dopant to diffuse from the glass into the polysilicon gate layer over the n-type region.
The known methods for forming high performance logic devices cannot be used to form high density DRAM where the transfer device is a surface channel PFET. It may be advantageous in a logic process to have a surface channel PFET transfer device as the MOSFET for a trench cell. This integrates well with the already existing P+ substrate normally used in high performance bulk silicon logic.
High density DRAM requires an insulating cap which is self-aligned to the gate conductor. This structure is necessary for forming bit line contacts which are borderless to adjacent word lines. A typical high density DRAM is shown in FIG.
2
. As can be seen from
FIGS. 1 and 2
, the present state of the art gate stack for high performance logic device consists of a single polysilicon gate conductor
4
,
5
, whereas the high density DRAM has a multi-layer gate stack
10
. The gate stack
10
of the DRAM typically comprises a polysilicon gate conductor
11
with a metal layer
12
formed thereon for lowering the resistance of the polysilicon gate. This gate structure is then entirely enclosed on all sides by a capping layer
13
. The capping layer
13
is provided so that the borderless contact stud
14
can be formed on the gate stack
10
, without shorting to it. This structure with the borderless contact stud is necessary to achieve the required high densities in DRAM cell arrays.
Current processes for forming logic devices do not provide for a self-aligned insulating cap and DRAM processes are not easily amenable to dual work function gate doping. Therefore, there is a need to provide dual work function gate conductors with a self-aligned insulating cap which can be readily made for merged high performance logic/high density DRAM applications. Additionally, the borderless contact can be applied to logic to increase their standard cell density (e.g. SRAM, adder, etc.)
SUMMARY OF THE INVENTION
A method for forming dual work function gate conductors with self-aligned insulating caps for merged high performance logic/high density DRAM applications is provided. In an embodiment of the invention, two additional layers are deposited on the polysilicon gate stack prior to the cap layer needed for a borderless contact. The additional layers are a barrier layer formed on the polysilicon gate and a dopant source, which can be activated and driven into the gate electrode at a later point in the process, formed on the barrier layer.
According to another embodiment of the invention, a gate insulating layer is formed on a substrate. An undoped layer of polysilicon is then deposited on top of the gate insulating layer and a barrier layer is formed on top of the polysilicon. A dopant of a first conductivity type is then implanted into selected areas of the polysilicon. Alternatively, the steps of forming the barrier layer and of implanting the dopant may be reversed if desired. Next, a second layer containing a dopant of a second conductivity type is formed on top of the barrier layer and a capping layer is formed over the second layer. Gate stacks are defined and etched and the dopant of the second conductivity type is driven from the second layer through the barrier layer into the polysilicon layer.
In another embodiment of the invention, a layer of silicide is formed between the polysilicon layer and the barrier layer.
According to another embodiment of the invention, the dopant is driven from the second layer through the barrier layer and into the underlying polysilicon by a hydrogen anneal.
In another embodiment of the invention, wet or steam oxidation is used to form an oxide layer on the sidewall of the gate stacks, as well as to help drive the dopant into the polysilicon due to the presence of hydrogen.
In another embodiment of the invention, a silicon nitride spacer is formed on the gate stacks after they have been defined and etched. The silicon nitride spacers are removed from selected gates in which it is desired to alter the doping of intrinsic polysilicon gate layer. Wet or steam oxidation is then performed to form the sidewalls, as well as to drive the dopant into the polysilicon in those gate stacks which had the silicon nitride spacers removed.
In a further embodiment, a multiple anneal process is used to form enhancement and depletion mode devices on the same substrate.


REFERENCES:
patent: 4997785 (1991-03-01), Pfiester
patent: 5393676 (1995-02-01), Anjum et al.
patent: 5599734 (1997-02-01), Byun et al.
patent: 5605861 (1997-02-01), Appel
patent: 5633177 (1997-05-01), Anjum
patent: 5681771 (1997-10-01), Hwang
patent: 5712176 (1998-01-01), Lytle et al.
patent: 5714398 (1998-02-01), Chao et al.
patent: 5747378 (1998-05-01), Fan et al.
patent: 5770490 (1998-06-01), Frenette et al.
patent: 5773358 (1998-06-01), Wu et al.
patent: 5937289 (1999-08-01), Bronner et al.
patent: 6030876 (2000-02-01), Koike
patent: 6127707 (2000-10-01), Chong et al.
patent: 52-043375 (1977-05-01), None
patent: 6177154 (1994-06-01), None
Bassous, E., “Methods For Fabricating P+ and N+ Poly-Si Gates In A Single Poly-Si Layer For MOSFE

Affiliated with

Also associated with

Rating

Dual work function gate conductors with self-aligned... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual work function gate conductors with self-aligned..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual work function gate conductors with self-aligned... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2540425