Dual word line or floating bit line low power SRAM

Details Dual word line or floating bit line low power SRAM Dual word line or floating bit line low power SRAM

2007-07-10

2009-06-09

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000

Reexamination Certificate

active

07545670

ABSTRACT:
Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and preventing the complementary bit line (BLC) from substantially dropping from a pre-charge level during operations in which a logic one is read from the anti-parallel storage circuit.

REFERENCES:
patent: 5040146 (1991-08-01), Mattausch et al.
patent: 5774393 (1998-06-01), Kuriyama
patent: 6097651 (2000-08-01), Chan et al.
patent: 7313012 (2007-12-01), Chuang et al.
patent: 7362606 (2008-04-01), Chuang et al.
patent: 7480170 (2009-01-01), Adams et al.

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