Dual word line mode for DRAMs

Details Dual word line mode for DRAMs Dual word line mode for DRAMs

2006-02-21

2006-02-21

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S187000, C365S188000

Reexamination Certificate

active

07002874

ABSTRACT:
An integrated circuit memory includes circuitry for individually activating word lines in a first one memory cell per bit operational mode, simultaneously activating at least two word lines in a second operational mode where two or more memory cells are dedicated to each data bit, and providing a word line sequence when first converting stored data in the array of memory cells from the first operational mode to the second operational mode. The word line sequence includes activating a first word line, developing a valid signal on a corresponding bit line, and then activating a second word line while the first word line is still active.

REFERENCES:
patent: 5574879 (1996-11-01), Wells et al.
patent: 5671388 (1997-09-01), Hasbun
patent: 6452855 (2002-09-01), Hsu et al.
patent: 6867994 (2005-03-01), Tsukikawa

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