Dual wired integrated circuit chips

Details Dual wired integrated circuit chips Dual wired integrated circuit chips

2011-05-10

2011-05-10

Richards, N Drew (Department: 2895)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With electrical contact in hole in semiconductor

C257S382000, C257S532000, C257S618000, C257S774000, C438S355000, C438S667000

Reexamination Certificate

active

07939914

ABSTRACT:
A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

REFERENCES:
patent: 3864755 (1975-02-01), Hargis
patent: 5589419 (1996-12-01), Ochiai
patent: 5918130 (1999-06-01), Hause et al.
patent: 5927993 (1999-07-01), Lesk et al.
patent: 6376351 (2002-04-01), Tsai
patent: 6392290 (2002-05-01), Kasem et al.
patent: 6429509 (2002-08-01), Hsuan
patent: 6562647 (2003-05-01), Zandman et al.
patent: 6562718 (2003-05-01), Xiang et al.
patent: 6583030 (2003-06-01), Grassl
patent: 6627953 (2003-09-01), Vu et al.
patent: 6921712 (2005-07-01), Soininen et al.
patent: 6921961 (2005-07-01), Sanchez et al.
patent: 7375389 (2008-05-01), Oh et al.
patent: 2003/0203546 (2003-10-01), Burbach et al.
patent: 2004/0145058 (2004-07-01), Marty et al.
patent: 2004/0150013 (2004-08-01), Ipposhi
patent: 2004/0183204 (2004-09-01), Cave et al.
patent: 2004/0266159 (2004-12-01), Gardecki et al.
patent: 2005/0042867 (2005-02-01), Sanchez et al.
patent: 2005/0044521 (2005-02-01), Swope
patent: 2005/0056881 (2005-03-01), Yeo et al.
patent: 2005/0156238 (2005-07-01), Wen et al.
patent: 2005/0167782 (2005-08-01), Sanchez et al.
patent: 2006/0095872 (2006-05-01), McElvain et al.
patent: 2007/0236986 (2007-10-01), Fifield et al.
patent: 2007/0245271 (2007-10-01), Feng et al.
patent: 05267563 (1993-10-01), None
patent: 06275803 (1994-09-01), None
patent: WO94/17553 (1994-08-01), None
patent: WO02/19421 (2002-03-01), None
Ichimori, Takashi; Hirashita, Norio, in “Fully-Depleted SOI CMOSFETs With the Fully-Silicided Source/Drain Structure,” Dec. 12, 2002, IEEE Transactions on Electron Devices, vol. 49, No. 12, 2296-2300.
Office Action (Mail Date Jan. 25, 2010) for U.S. Appl. No. 11/939,582, filed Nov. 14, 2007; Confirmation No. 6263.
H. Eggers, K. Hieber; Recent Development in Multilevel Interconnect Technology, May 1987, Component Division, Technology Center for Microelectronics, Siemens AG, Munich, W-Germany. 6 pages.
Office Action (Mail Date Jul. 7, 2010) for U.S. Appl. No. 11/939,582, filed Nov. 14, 2007; Confirmation No. 6263.
Office Action (Mail Date Oct. 5, 2010) for U.S. Appl. No. 11/939,582, filed Nov. 14, 2007; Confirmation No. 6263.
Office Action (Mail Date Oct. 7, 2010) for U.S. Appl. No. 12/029,575, filed Feb. 12, 2008; Confirmation No. 9118.
Nov. 29, 2010 filed Appeal Brief and Supplemental Amendment for U.S. Appl. No. 11/939,582, filed Nov. 14, 2007; Confirmation No. 6263.

Affiliated with

Also associated with

Rating

Dual wired integrated circuit chips does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual wired integrated circuit chips, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual wired integrated circuit chips will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2679186