Static information storage and retrieval – Systems using particular element – Semiconductive
Reexamination Certificate
1999-03-03
2001-01-30
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Semiconductive
C365S184000, C365S182000, C365S156000, C365S154000
Reexamination Certificate
active
06181608
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to integrated circuits and, more particularly, to memory cells with dual threshold voltages and bitline leakage control.
2. Background Art
Static random access memory (SRAM) cells typically provide memory storage for bits that can be rapidly read from and written to. A typical SRAM cell has six field effect transistors (FET transistors). Two of the FET transistors form a first inverter and two of the FET transistors form a second inverter, between power and ground terminals. The first and second inverters are cross-coupled such that at a first storage node, the output of the second inverter is tied to the input of the first inverter, and at a second storage node, the output of the first inverter is tied to the input of the second inverter. The first and second cross-coupled inverters form latched wherein one of the storage nodes is pulled low and the other storage node is pulled high. The other two of the six transistors are pass FET transistors controlled by a wordline signal on a wordline conductor. One of the pass transistors is coupled between a bitline and the first storage node. The other pass transistor is coupled between a bitline# and the second storage node. With the pass transistors off, the first and second storage nodes are insulated from the bitline and bitline#, although there may be some leakage.
In a reading procedure, data and data# signals are precharged high on the bitline and bitline#, respectively. When the wordline is asserted, one of the storage nodes is low and the other is high. The low storage node begins to pull either the data or data# signal low depending on the state of the memory cell. A sense amplifier senses a difference between the data and data# signals and accelerates the fall of whichever of the data or data# signals corresponds to the low storage node until the storage node is low. The high storage node remains high and the sense amplifier may pin the storage node high through the data or data# signal (depending on the state of the memory cell). Accordingly, the reading procedure causes the storage nodes to remain at the same logic states after the wordline signal is de-asserted. The sense amplifier provides a signal indicative of the state.
In a writing procedure, circuitry in a sense amplifier causes one of the data or data# signals to be high and the other to be low in response to whether a high or low value has been written into a write buffer. When the wordline signal is asserted, if the current state of the first and second storage nodes is the same as that of the data and data# signals, then the first and second storage nodes remains the same. If the current state of the first and second storage nodes is different than that of the data and data# signals, one of the storage nodes is pulled down while the other storage node is pulled up. When the states of the first and second storage nodes in the latch formed of the two cross-coupled inverters changes, the latch is said to flip states.
Unlike dynamic random access memory (DRAM) cells, SRAM cells are not required to be refreshed to maintain their state. Rather, as long as the power is supplied to the power terminal and absent leakage, the voltage states of the first and second storage nodes are stable in the latch of the cross-coupled inverters.
However, to a greater or lesser extent, leakage is present in SRAM cells. To keep leakage low, the threshold voltages are kept relatively high. For example, the threshold voltages of transistors of the memory cells may be higher than for transistors of other portions of the integrated circuits containing the memory cells. However, keeping the threshold voltage high also decreases the switching speed and cache performance. Accordingly, there is a need for a structure and technique that allows for memory cells with low leakage and fast access.
SUMMARY
In some embodiments, the invention includes an integrated circuit including a bitline and a bitline#, wordlines, and memory cells. The memory cells each corresponding to one of the wordlines and each include first and second pass transistors coupled between first and second storage nodes, respectively, and the bitline and bitline#, respectively, the corresponding wordline being coupled to gates of the first and second pass transistors. The memory cells include first and second inverters cross-coupled between the first and second storage nodes, wherein the first and second pass transistors each have a lower threshold voltage than do transistors of the first and second inverters. Wordline voltage control circuitry coupled to the wordlines selectively controls wordline signals on the wordlines.
In some embodiments, the wordline voltage control circuitry asserts the wordline signal for a selected wordline corresponding to a memory cell selected to be read and underdrives the wordline signals for the wordlines not corresponding to the selected memory cell.
REFERENCES:
patent: 5020029 (1991-05-01), Ichinose et al.
patent: 5153852 (1992-10-01), Terrell
patent: 5222039 (1993-06-01), Vinal
patent: 5452246 (1995-09-01), Kawashima
patent: 5461713 (1995-10-01), Pasucci
patent: 5471421 (1995-11-01), Rose et al.
patent: 5583821 (1996-12-01), Rose et al.
patent: 5732015 (1998-03-01), Kazerounian et al.
patent: 5790452 (1998-08-01), Lien
patent: 5790461 (1998-08-01), Holst
patent: 5828597 (1998-10-01), Madan
patent: 5837573 (1998-11-01), Guo
patent: 5939762 (1999-08-01), Lien
patent: 403290893 (1991-12-01), None
I. Fukushi et al., “A Low-Power SRAM Using Improved Charge Transfer Sense Amplifiers and a Dual-Vth CMOS Circuit Scheme,” 1998 Symposium on VLSI Circuits Digest of Technical Papers, Jun. 11, 1998, pp. 142-145.
Y. Nakagome, “Voltage Regulator Deisgn for Low Voltage DRAMs,” Memory Design and Evolution, 1998 VLSI Memory Short Course, 1998 Symposium on VLSI Circuits, Jun. 10, 1998, pp. 1-40 (especially p. 37).
De Vivek K.
Keshavarzi Ali
Ye Yibin
Zhang Kevin
Aldous Alan K.
Intel Corporation
Nguyen Viet Q.
LandOfFree
Dual Vt SRAM cell with bitline leakage control does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dual Vt SRAM cell with bitline leakage control, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual Vt SRAM cell with bitline leakage control will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2512749