Dual voltage level shifted, cascoded current mirror

Amplifiers – With semiconductor amplifying device – Including current mirror amplifier

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323315, H03F 316

Patent

active

055898009

ABSTRACT:
A current mirror circuit (40) includes a first pair of mirrored transistors (T.sub.1 and T.sub.2) having common gate and source connections; a second pair of cascoded transistors (T.sub.3 and T.sub.4) with common gate connections, respectively connected in series between the first pair transistors (T.sub.1 and T.sub.2) and input and output voltage terminals (+V.sub.IN and +V.sub.OUT). First and second voltage level shifter circuitries (41,42) establish shifted bias voltages respectively at the first and second pair transistor gate connections. The first voltage level shifter comprises a pair of transistors (T.sub.5 and T.sub.6) connected in series between an applied voltage terminal and the second pair transistor source connections, for establishing a shifted biasing voltage at the second pair transistor gate connection. The second voltage level shifter comprises a pair of transistors (T.sub.7 and T.sub.9) connected in series between the applied voltage terminal and the first pair transistor source connections, for establishing a bias voltage at the first pair transistor gate connections.

REFERENCES:
patent: 4471292 (1984-09-01), Schenck et al.
patent: 4583037 (1986-04-01), Sooch
patent: 5311115 (1994-05-01), Archer
Babanezhad, J. N. and Gregorian, R., A Programmable Gain/Loss Circuit, IEEE Journal of Solid-State Circuits, vol. SC-22, No. 6, Dec., 1987, pp. 1082-1090.
Alvarez, A. R., Aspen Semiconductor Corp., BiCMOS Technology and Applications, Kluwer Academic Publishers, 1989, pp. 290-293.
Gray, P. R. and Meyer, R. G., University of California, Analysis and Design of Analog Integrated Circuits, John Wiley & Sons, 1977, pp. 197-261.

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