Dual/triple redundant computer system

Details Dual/triple redundant computer system Dual/triple redundant computer system

2006-05-16

2006-05-16

Beausoleil, Robert (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S010000, C714S012000

Reexamination Certificate

active

07047440

ABSTRACT:
A dual/triple redundant computer system having in one of the preferred embodiments triple redundant I/O modules and dual redundant central processor modules (CPM) that operate in parallel executing the same application program. Each input module includes three input circuits operating in parallel. The first CPM receives input data from first and third input circuits and transmits input data of the first input circuit to the second CPM. The second CPM receives input data from second and third input circuits and transmits input data of the second input circuit to the first CPM. Each CPM then performs a two-out-of-two vote among input data produced by first, second, and third input circuits and utilizes an outvoted data as input to the application program to provide output data by execution of the application program.Each output module includes three microcontrollers operating in parallel. First and second microcontroller receives output data respectively from first and second CPM, while a third microcontroller receives at the same time output data from both first and second CPM. First microcontroller transmits output data to a first and a second output circuit. Second microcontroller transmits output data to second and third output circuit. The third microcontroller performs a selected logic operation among output data produced by first and second CPM and then transmits a result of this operation to third and first output circuits. Each output circuit generates a logical product of output data received from two associated microcontrollers. Outputs of first, second, and third output circuit are connected to each other for providing a two-out-of-three voting among output data produced by first, second, and third microcontroller, and for allowing the system to generate a system output as a result of a two-out-of-two voting of output data generated by first and second central processor modules.

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