Dual track/stepper interface configuration for wafer processing

Details Dual track/stepper interface configuration for wafer processing Dual track/stepper interface configuration for wafer processing

2000-05-30

2002-04-09

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C396S611000

Reexamination Certificate

active

06368985

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a method and apparatus for manufacturing a semiconductor integrated circuit (“IC”). More specifically, this invention relates to an improved method and apparatus for processing semiconductor wafers with a dual track and stepper.
BACKGROUND OF THE INVENTION
The present invention applies particularly to the fabrication of semiconductor integrated circuits. Some examples of these semiconductor integrated circuits comprise non-volatile memory integrated circuits. Non-volatile memory integrated circuits include an EPROM, an EEPROM, a flash memory device, and a complementary metal oxide silicon (“CMOS”) type device. Exemplary devices may comprise field-effect transistors (“FET”) containing a gate over gate insulator over silicon (“MOSFET”), as well as other ultra-large-scale integrated-circuit (“ULSI”) systems.
Integrated circuits are utilized in a wide variety of commercial and military electronic devices, including, e.g., hand held telephones, radios and digital cameras. The market for these electronic devices continues to demand devices with a lower voltage, lower power consumption and a decreased chip size. Also, the demand for greater functionality is driving the “design rule” lower, for example, into the sub-half micron range.
These integrated circuit devices are generally fabricated in groups on a semiconductor wafer. During fabrication, a photolithographic process is utilized to form various components and structures. The components and structures are formed according to a photolithographic pattern provided on the semiconductor wafer. This photolithographic process is conventionally utilized in the front end portion of a semiconductor wafer production. There are three basic steps involved in the photolithography processing of each semiconductor wafer. First, a photoresist is applied to each wafer in a coater. Each wafer is then exposed to a radiation source in a stepper, and finally each exposed wafer is developed in a photoresist developer. Since the IC are typically multilayered, this process is repeated a number of times.
More specifically, in a portion of the photolithography of these wafers, a photoresist coater and developer system is utilized in the patterning of various layers of the wafer that will form the circuit device. The photoresist coater and developer system applies, or coats, a light-sensitive resin, i.e., a photoresist layer, to wafers by depositing a pre-selected amount of the photoresist solution. Next, the system spins the wafers at a relatively high rate of speed to distribute the photoresist into a relatively even coating over the wafer. Then, the wafers are baked to induce a volatization of a casting solvent in the photoresist. Next, the wafers are exposed to a light source in a stepper, e.g., a deep ultraviolet (“DUV”) light source, for patterning. The exposed wafers are then developed by a chemical treatment, and are again baked to dry the wafers.
Conventional examples of resist coater and developer systems, e.g., are the Tokyo Electron Limited (TEL) sub-half micron compatible Coater/Developer Clean Track systems. Conventional systems may include a chemically amplified resist (“CAR”) in the deep ultraviolet (“DUV”) process that has been adopted for the sub-half micron design rule type of circuit devices. The combination of the coater and developer is typically referred to as a “track.”
As to the development of the photoresist that has been formed on the wafer, conventionally, a chemical developer is utilized to remove areas defined in the steps of masking and exposure of the photoresist layer that has been deposited on the wafer. The development of the photoresist is an important part of the wafer fabrication.
For example, in sub-half micron semiconductor processing, one of the most important parameters in the photolithography area is the critical dimension (“CD”). The above described relatively complex integrated circuits will only function as designed if the critical dimensions are within specification. There are many parameters that control the critical dimension. One of these parameters comprises the time interval between the application of the photoresist in the coater and the exposure of the wafer in the stepper.
Wafers may be processed in either a batch or interface mode. In the batch mode a number (25 for example) wafers may be processed together such that a photoresist is applied to each of the wafers individually. Depending on the process, the time between the application of the photoresist to the first wafer to be processed and the last wafer may be 45 minutes. Once the photoresist has been applied to all of the wafers, each wafer is then individually exposed in the stepper. After all of the wafers have been exposed, then each wafer is developed in the developer.
In the interface mode, each wafer is coated with a photoresist and then sent to the stepper to be exposed. Since the time interval required to expose each wafer in the stepper is less than the time required to apply the photoresist in the coater, no queue develops between the coater and the stepper. However, the time required to develop each wafer is longer than the time required to expose the wafer in the stepper. As a result a queue develops between the stepper and the developer.
As discussed above, IC's are often multi-layered. Accordingly, once the lot of wafers has been processed, the process of photoresist application, exposure, and developing is repeated on the lot until the IC's are completed. The type of photoresist that is applied for each layer of the IC may be different than the previous photoresists that have been applied. Additionally, a different type of photoresist may require a different developer material. For example, a track may include the ability to apply three different photoresists in a single coater, and two different developer materials in the developer. The number of photoresists and developer materials available is a function of the number of nozzles designed into the system. Additionally, a different image is used to expose the wafers for each layer of the IC. The image exposed on the wafer is formed on a reticle used in the imaging process.
Some different photoresists react with one another and coagulate. This can result in clogging the drainage of the coater station. As a result, either the drainage system must be cleaned periodically to prohibit the system from backing up, or the wafers must be processed on a separate track and stepper line.
A typical setup includes a track having a coater and a developer that is connected to a single stepper. The various components communicate via software that coordinates the processing of the wafers in the coater, stepper and developer. A conventional wafer transfer system includes a plurality of cassettes used to store the wafers both before and after they are processed in the coater, stepper or developer. In the batch mode, a group of wafers is stored in a cassette. Automated equipment moves each wafer from the cassette for processing in the given station and then replaced to the cassette when complete. The entire cassette may then be moved manually by an operator to the next station for processing. The entire system may be automated utilizing lateral feeders and conveyor belts, thereby permitting the wafers to be processed in the interface mode.
Alternatively, as described in U.S. Pat. No. 5,455,894, assigned to a common assignee, the wafer transfer system may include a computer controlled robotic interface unit having a robotic arm that moves the wafers without the need for conveyor belts. The '894 patent is included herein by reference.
The cost of the stepper may be six time the cost of the coater and developer track unit. Since the stepper processes the wafers more quickly than the coater and developer, the stepper is often idle. Additionally, maintenance is required on the coater and developer more often than the stepper. Since the stepper is dedicated to a specific track, the stepper will be idled during the periodic main

Affiliated with

Also associated with

Rating

Dual track/stepper interface configuration for wafer processing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual track/stepper interface configuration for wafer processing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual track/stepper interface configuration for wafer processing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2874934