Static information storage and retrieval – Read/write circuit
Reexamination Certificate
2000-12-08
2001-09-25
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
C365S156000, C365S205000
Reexamination Certificate
active
06295232
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a read circuit for storage cells of a semiconductor storage array including dual-to-single-rail conversion. The invention also relates to a method for converting dual bitline read signals to single bitline read signals.
BACKGROUND OF THE INVENTION
Static VSLI semiconductor storage arrays use a single or dual bitline read scheme. Single bitline circuits allow a high density on the cost of noise immunity and performance. This applies in particular to large storage arrays. Dual bitline circuits which use true and complement bitlines for reading out the storage cells are faster and show a higher noise immunity but need more area on the semiconductor chip. Such circuits include a special read head for sensing the voltage difference on the bitlines and convert it to a single data out signal (U.S. Pat. No. 5,949,723).
Known dual bitline read circuits include a bit select circuit, a read head circuit and additional circuits which are required to compensate signal level differences and to achieve full logical signal levels for one and zero bits to produce a reliable data read out. The bit select circuit selects one of a plurality of bitline pairs of those storage cells which are activated by the same word line for a read operation. The storage cells drive the bitlines to full “zero” signals and weak “one” signals respectively where a weak “one” signal is represented by the supply voltage level VDD reduced by the thereshold voltage of the NFET pass device. A bitline swing control circuitry and additional circuitry in the read head circuit is used to compensate this asymmetry.
The bitline swing control circuitry force the bitlines to an intermediate voltage level to reduce the swing of the bitline signals the storage cell has to drive and thereby speeds up the read cycle. The function of the read head circuit is to sense the voltage level difference between the bitlines and to combine the dual read bitlines to a single bitline which is connected to the data out driver. The read head provides an indirect coupling of the bitlines by two cross-coupled PFET devices. This circuitry serves to develop full ‘one’ and ‘zero’ signals for being fed to the data out driver. However, the operation of the cross-coupled PFET devices burdens the speed at which the bit signals are developed. The operation of a known dual bitline read circuit of this type is explained below in more detail with reference to FIG.
1
.
SUMMARY OF THE INVENTION
It is an object of the invention to improve the performance of dual bitline read circuits without decreasing the reliability of the data read out.
It is a further object of the invention to shift the signal levels on the bitlines to a symmetrical ratio and to improve “weak one” read out signals. It is also an object of the invention to avoids a standby current within the read circuit. According to the invention, as defined in the claims, a read circuit of the type described above and shown in
FIG. 1
is improved by avoiding an indirect coupling of the bitlines by cross-coupled PFET devices, and provides instead a direct coupling of the bitlines to reduce the period of generating the bit signals as input of the data out driver.
The read head circuit of the invention comprises an inverter in a first one of the bitlines which turns a ‘weak one’ signal to a full ‘zero’ signal. The bit select circuit is integrated into the read head by connecting a second bitline through a first bit select switch to the output of the read head circuit and by connecting the output of the inverter through a second bit select switch to the output of the read head circuit.
According to further aspects of the invention the first bit select switch is a NFET device and the second bit select switch is a PFET device. The first bitline may be assigned to the complement output of the cell and the second first bitline may be assigned to the true output of the cell.
According to a further aspect of the invention said inverter may be part of a feedback loop from the output of the inverter to its input including a PFET switch which is controlled by the output of the inverter and additionally improves the ‘one’ input level of the inverter and serves to eliminate any DC current in the inverter.
Furthermore, according to another aspect of the invention the input of the inverter is connected to a first one of the bitlines to turn a ‘weak one signal to a full zero signal, and its output is directly combined with the second bitline. Such implementation may be used for storage cell arrays the bit columns of which are not divided into sub-columns and therefore do not need a bit select circuitry.
The invention also provides a method for converting dual bitline read signals to single bitline read signals by inverting the read signals on a first one of the bitlines for turning a ‘weak one’ read signal into a full ‘zero’ signal and by directly combining the output signals of the inverted read signal with the read signals of the second one of the bitlines.
REFERENCES:
patent: 5715210 (1998-02-01), Yoo et al.
patent: 5986923 (1999-11-01), Zhang et al.
Helwig Klaus
Pille Juergen
Wendel Dieter
Hoang Huan
International Business Machines - Corporation
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