Dual threshold voltage and low swing domino logic circuits

Details Dual threshold voltage and low swing domino logic circuits Dual threshold voltage and low swing domino logic circuits

2005-05-31

2005-05-31

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S121000

Reexamination Certificate

active

06900666

ABSTRACT:
A domino logic circuit is configured to reduce power consumption. In a first embodiment, a sleep switch grounds the dynamic node during sleep mode. In a second embodiment, a low-swing circuit at the output reduces the output and keeper transistor gate voltage swings. A third embodiment combines those two techniques.

REFERENCES:
patent: 5973541 (1999-10-01), Rajivan et al.
patent: 6049231 (2000-04-01), Bosshart
patent: 6429689 (2002-08-01), Allen et al.
patent: 6522171 (2003-02-01), Hanson et al.
patent: 6580293 (2003-06-01), Bernstein et al.
Alvandpour et al., A Low-Leakage Dynamic Multi-Ported Register File in 0.13 μm CMOS, ISLPED '01, Aug. 6-7, 2001, Huntington Beach, California, © 2001 ACM, pp. 68-71.
Tschanz et al.,Effectiveness of Adaptive Supply Voltage and Body Bias for Reducing Impact of Parameter Varitations in Low Power and High Performance Microprocessors, 2002 Symposium on VLSI Circuits Digest of Technical Papers, © 2002, IEEE, pp. 310-311.
Keshavarzi et al., Technology Scaling Behavior of Optimum Reverse Body Bias for Standby Leakage Power Reduction in CMOS IC's, ISLPED '99, San Diego, California, © 1999, ACM, pp. 252-254.
Keshavarzi et al., Forward Body Bias for Microprocessors in 130nm Technology Generation and Beyond, 2002 Symposium on VLSI Circuits Digest of Technical Papers, © 2002 IEEE, pp. 312-315.
Wann et al., CMOS with Active Well Bias for Low-Power and FR/Analog Applications, 2000 Symposium on VLSI Technology Digest of Technical Papers, © 2000, IEEE, pp. 158-159.
Huang et al., Scalability and Biasing Strategy for CMOS with Active Well Bias, 2001 Symposium on VLSI Technology Digest of Technical Papers, pp. 107-108 , 2001.
Alvandpour et al., A Sub-130-nm Conditional Keeper Technique, IEEE Journal of Solid-State Circuits, vol. 37, No. 5, May 2002, pp. 633-638.
Nowka et al., Circuit Design Techniques for a Gigahertz Integer Microprocessor, proceedings of the IEEE International Conference on Computer Design, VLSI in Computers and Processors, pp. 11-16, Oct. 1998.
Kursun et al., Low Swing Dual Threshold Voltage Domino Logic, Proceedings of the ACM/SIGDA Great Lakes Symposium on VLSI, Apr. 2002, pp. 47-52.
Hwang et al., Ultrafast Compact 32-bit CMOS Adders in Multiple-Output Domino Logic, IEEE Journal of Solid-State Circuits, vol., 24, No. 2, Apr., 1989, pp. 358-369.
Allam et al., High-Speed Dynamic Logic Styles for Scaled-Down CMOS and MTCMOS Technologies, Proceedings of the IEEE International Symposium on Low Power Electronics and Design, Jul., 2000, pp. 155-160.
Alvandpour et al., A Leakage-Tolerant Multi-Phase Keeper for Wide Domino Circuits, © 1999 IEEE, pp. 209-212.

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