Dual threshold SRAM cell for single-ended sensing

Details Dual threshold SRAM cell for single-ended sensing Dual threshold SRAM cell for single-ended sensing

2000-09-29

2003-02-11

Phan, Trong (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S203000

Reexamination Certificate

active

06519176

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention.
The invention relates to the field of static random-access memory (SRAM) cells and memory arrays.
2. Prior Art and Related Art
As semiconductor processes scale and improve, permitting smaller critical dimensions and lower supply voltages, logic circuit delays decrease in the order of 30% in each generation of new technology. Unfortunately, the delay in bit lines and sense amplifiers in high performance on-chip caches using differential low-swing sensing does not improve at the same rate. This is because the offset sensing voltage in the sense amplifier does not proportionately change with each generation and the bit line leakage limits the threshold voltage scaling. The resultant divergence between logic circuit delay and bit line delay has lead to the use of single-ended full-swing sensing which does scale with each new technology generation instead of the more traditional differential sensing.
With differential sensing, typically 100 mV difference between the complementary bit lines is sufficient for sensing. This relatively low swing provides fast sensing. However, as the passgate transistors which couple the bistable circuit to the complementary bit lines scale, leakage increases. This increase in leakage through the unselected cells makes sensing more difficult. One solution to this problem is to decrease the number of cells connected to each pair of bit lines and thereby impacting the number of rows in the cache and its architecture. For instance, reducing the number of cells from 128 to 64 or even 32 cells in order to minimize the leakage provides a solution. This however, complicates the overall memory design. Another solution to this problem is described in co-pending application Ser. No. 09/261,915 (filed Mar. 3, 1999) entitled “Dual VT SRAM Cell with Bit Line Leakage Control,” now U.S. Pat. No. 6,181,608.
Another approach to the scaling problem is to use single-ended full-swing sensing. Here, one of the bit lines swings, for instance, to 50% or so of the Vcc potential before sensing occurs. An example of a single-ended sense amplifier is described in “Reference-Free Single-Ended Clocked Sense Amplifier Circuit,” Ser. No. 09/302,677 (filed Apr. 30, 1999 now U.S. Pat. No. 6,137,319.
In both the single-ended and differential mode sensing schemes conventional high-threshold voltage SRAM cells and dual voltage SRAM cells are used. With the dual voltage SRAM cells, the passgate transistors coupling the cell to the bit line have a lower threshold voltage than other transistors in the memory array. While this speeds up sensing, it degrades noise margins in single-ended sensing. What is needed is to decrease leakage without increasing delay.


REFERENCES:
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patent: 5134581 (1992-07-01), Ishibashi et al.
patent: 6061267 (2000-05-01), Houston
patent: 6137319 (2000-10-01), Krishnamurthy et al.
patent: 6181608 (2001-01-01), Keshavarzi et al.

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