Dual threshold gate array or standard cell power saving...

Details Dual threshold gate array or standard cell power saving... Dual threshold gate array or standard cell power saving...

2001-10-01

2003-12-23

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06668358

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to Complimentary Metal Oxide Semiconductor (CMOS) Application Specific Integrated Circuit (ASIC) libraries, and in particular to reduction of power dissipated in such libraries where multiple threshold options are available for the Field Effect Transistors (FETs) used in the libraries.
BACKGROUND OF THE INVENTION
The history of computer and related electronic circuitry has seen a constant movement to faster and lower powered circuits. In computers of the early 1950's, vacuum tubes were used as the switching elements. Vacuum tubes operated by heating a cathode with a filament, causing thermionic emission of electrons, which were then attracted to an anode biased positively relative to the cathode. Applying a low voltage on a control grid placed between the cathode and the anode could halt flow of the electrons. The heating requirement caused large amounts of static power to be dissipated. Static power is power dissipated independent of switching activity, and occurs whether the vacuum tube is in a conducting or a nonconducting state, or both.
Vacuum tubes were replaced in time by circuits comprising bipolar transistors. The dominant logic circuit families were Transistor Transistor Logic (TTL) and Emitter Coupled Logic (ECL). Both of these types of circuits also dissipated static power. ECL, in particular, was known for high power requirements. Computers implemented in TTL or ECL logic families dominated the 1960 to 1990 time frame. Increasingly elaborate cooling techniques were created to cool the computers of that era. Computers such as the IBM 3081 used pistons pressed against the semiconductor logic chips to remove heat from the chips. The heat was then transferred from the pistons to a heat sink. The heat sink was water-cooled.
CMOS logic circuits came into wide use in computer systems in the 1990s. CMOS in the 1990s was characterized by relatively high supply voltage. 5.0 volts, 3.3 volts, 2.5 volts, and 1.8 volts were commonly used for the supply voltage. These supply voltages allowed for the FET thresholds to be relatively high while still supporting relatively high performance. The amount of current an FET conducts, and therefore the performance, is strongly dependent on the supply voltage minus the FET threshold voltage. If the supply voltage is reduced, it is advantageous, therefore, to also reduce the FET threshold.
FETs with high thresholds have negligible leakage when the FET is “off”, that is, the FET gate voltage is set such that the FET does not conduct. In the “off” case of an N-channel FET (NFET), the gate voltage would be set at a low voltage, usually ground. In the case of a P-channel FET (PFET), the gate voltage would be set at a high voltage, usually the supply voltage. CMOS logic circuits constructed of such FETs dissipate very little static power. Properly designed CMOS logic circuits have either a conducting path to ground through an NFET network, or a conducting path to the supply voltage through a PFET network. During a switch, CMOS circuits do have a brief time when both the NFET network and the PFET network are partially conducting. Current flowing from the supply voltage to ground during this time is called shoot-through current. Except for power associated with shoot-through current, power in such CMOS logic is almost totally dynamic power, which charges and discharges capacitances of gates, wiring, and parasitic device capacitances. Dynamic power in CMOS is usually calculated with the equation, P=½*C*V*V*f, where P is the dynamic power, C is the amount of capacitance switched, V is the supply voltage, and f is the frequency at which the capacitance is switched.
It is immediately apparent from the equation that lowering the supply voltage can dramatically reduce the dynamic power. Supply voltage has indeed been lowered over the years, from 5 volts to 3.3 volts to 2.5 volts, to 1.8 volts. Although in a given technology, performance will degrade with reduced supply voltage, performance has been maintained or improved by advancing the FET technology. Some of the advances have included making the FET channels shorter, making the FET gate oxides thinner, and reducing the FET thresholds.
A problem has recently arisen as decreasing supply voltage approaches 1.0 volt. Maintaining performance has required reduction of FET thresholds to the point that, even when the device is “off”, substantial subthreshold leakage occurs. This leakage causes power dissipation that has become a significant percentage of the total power of a logic chip.
A number of CMOS processes have begun to offer multiple, usually two, FET threshold options. This is called Dual VT technology. FET threshold voltage is called VT. The FETs with higher thresholds (high VT) are slower than the FETs with lower thresholds (low VT). FET threshold differences can be accomplished in several ways, such as varying the doping in the silicon, or lengthening the channels of FETS where a higher threshold is desired. Previous work has led to methods that use Dual VT technology in custom integrated circuits to reduce the subthreshold leakage. “Static Power Optimization of Deep Submicron CMOS Circuits for Dual VT Technology”, by Qi Wang and Sarma B. K. Vrudula, of the Center for Low Power Electronics, ECE Department, University of Arizona, Tucson, Ariz. 85721, describes an algorithm for assignment of an FET with a higher VT in places where performance will not be compromised. Another previous effort applicable in custom circuit design is “An Enhanced Dual Threshold Voltage Leakage Control Technique for a Sub-500PS 64-bit Adder”, by Lizhi Charlie Zhong and Hongjing Zou. Yet a third previous effort applicable in custom circuit design is “A Static Power Model for Architects”, by J. Adam Butts and Gurindar S. Sohi.
All of the above efforts apply higher VT FET devices in a custom circuit design to reduce static power.
Much of the logic used in today's computers and related equipment use ASICs. An ASIC design system provides a designer with a predesigned set, or library, of logic blocks. The designer builds the desired logic function on the chip by selecting from the library and specifying the interconnection of the blocks. The design system further provides rules governing valid interconnection topologies, delay computation, system timing, and other control or checking information needed to guarantee functionality of the logic function of the chip. Since all of the blocks in the library are predesigned, the ASIC designer has no ability to change the circuit design of any of the blocks. Therefore, the algorithmic selection of FET thresholds available to the custom circuit designers as referenced above is not available to the ASIC designer.
Therefore, a need exists to give the ASIC designer the capability to reduce static power in a Dual VT technology ASIC design system by providing appropriate Dual VT circuit logic blocks in the ASIC library, and a method to select and use those blocks effectively.
SUMMARY OF THE INVENTION
A principal object of the present invention is to reduce the average subthreshold leakage current on ASIC chips by providing a set of low leakage logic blocks that are functionally equivalent to other logic blocks that are faster, but which have significant leakage currents, and substituting the low leakage logic blocks where timing margin permits.
In brief, a method and a set of low leakage logic blocks are provided. The method initializes all instantiations of logic blocks on the chip to the faster, but leaky, versions of the logic blocks. All delays on the chip are computed. All timing margins (slacks) are computed for all inputs and outputs of each instantiation.
Each inverter logic block is then considered for replacement by a low leakage version of the inverter function. The replacement will be done and made permanent if timing margin permits.
After all inverters on the chip are considered, two input NANDs, and, optionally, two input NORs, are considered. In this part of the method, an attempt is made to replace each

Affiliated with

Also associated with

Rating

Dual threshold gate array or standard cell power saving... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual threshold gate array or standard cell power saving..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual threshold gate array or standard cell power saving... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3116377