Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
1999-11-18
2001-09-25
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S737000, C174S050510, C174S260000
Reexamination Certificate
active
06294840
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor chip device assembly, and in particular to flip chip package construction. More specifically, the invention relates to improvements in the construction of semiconductor flip chip packages directed to optimizing the standoff height between an IC chip and a packaging substrate.
DESCRIPTION OF THE RELATED ART
In semiconductor device assembly, an integrated circuit (IC) chip or “die” may be bonded directly to a packaging substrate, without the need for a separate leadframe or for separate I/O connectors (e.g. wire or tape). Such chips are formed with ball-shaped beads or bumps of solder affixed to their I/O bonding pads. During packaging, the chip is “flipped” onto its active circuit surface so that the solder balls form electrical connections directly between the chip and conductive traces on a packaging substrate. Semiconductor chips of this type are commonly called “flip chips.”
FIGS. 1A
,
1
B and
1
C illustrate stages in a conventional method for packaging a semiconductor flip chip, in which a chip and a packaging substrate are electrically connected and mechanically bonded.
FIG. 1A
shows a cross-sectional, side view of an unbonded flip chip with the chip
100
having an active circuit surface
102
on which are arranged solder balls
104
. The solder may be composed of a low melting point eutectic material or a high lead material, for example. It should be noted that this figure and the figures that follow are intended to be representative and to emphasize features of the present invention, and, for example, do not show the solder balls in proportion to the chip. In current designs, the chip may have dimensions on the order of 0.5×0.5 inch (1 inch=2.54 cm) whereas the unbonded solder balls may have a diameter on the order of 4 to 5 mils (about 100-125 microns) with a pitch
105
of about 250 microns.
Prior to bonding the chip
100
to a packaging substrate, a solder mask
101
is applied to the packaging substrate surface
103
. The solder mask performs several functions, including providing electrical insulation resistance between the circuit traces on the substrate, chemical and corrosion resistance or protection, mechanical (scratch, wear) protection, boundaries on solder surfaces, and filling blind and through-hole vias in the substrate. Conventional solder masks are applied as singlestep (single or multiple pass) solder mask layers by screening a wet film onto the packaging substrate surface and then curing the film by oven baking. The wet film can be screened in a pattern or photo-sensitive materials can be used to pattern features into the cured film in order to expose bond pads for making the appropriate electrical connections with the die to be mounted on the package substrate.
Following the application and patterning of the solder mask, solder flux (not shown) is applied to either the active surface
102
of the chip
100
or the packaging substrate surface. The flux serves primarily to aid the flow of the solder, such that the solder balls
104
make good contact with pads on the packaging substrate. It may be applied in any of a variety of methods, including brushing or spraying, or dipping the chip
100
into a thin film, thereby coating the solder balls
104
with flux. The flux generally has an acidic component, which removes oxide barriers from the solder surfaces, and an adhesive quality, which helps to prevent the chip from moving on the packaging substrate surface during the assembly process.
As shown in
FIG. 1B
, after the flux is applied, the chip
100
is aligned with and placed onto a placement site on the packaging substrate
106
such that the chip's solder balls
104
are aligned with electrical bonding pads
107
or traces on the substrate
106
. The substrate is typically composed of a laminate or organic material, such as fiber glass, PTFE (such as Teflon™, available form Gore, Eau Claire, Wisc.) BT resin epoxy-fiberglass laminates or ceramic-plastic composites. Heat (to a temperature of about 220EC, for example) is applied to one or more of the chip
100
and the packaging substrate
106
, causing the solder balls
104
to reflow and form electrical connections between the chip
100
and the packaging substrate
106
. Then, the remaining flux residue is substantially removed in a cleaning step, for instance by washing with an appropriate solvent.
Currently, the thickness
110
of the single-step solder mask
101
is about 30 to 40 microns (typically about 35 microns) while the pads
107
are about 15 to 20 microns in height. A typical gap
109
between the chip
100
and the top of the solder mask
101
on the packaging substrate
106
is about 70 to 80 microns, with the distance
112
between the chip and the bonding pads being about the diameter of the solder balls, typically about 115 microns.
At this point, the mechanical bonding procedure can begin. An underfill material, typically a thermo-set epoxy
108
, such as is available from Hysol Corporation of Industry, California (product numbers 4511 and 4527), Ablestik Laboratories of San Jose, Calif., and Johnson Matthey Electronics of San Diego, Calif., is dispensed into the remaining space (or “gap”)
107
between the chip
100
and the substrate
106
. In a typical procedure, beads of thermo-set epoxy, are applied long one edge of the chip where the epoxy is drawn under the chip by capillary action until it completely fills the gap between the chip and the packaging substrate. In order to ensure reliable operation of the completed package, it is important that the underfill material
108
be uniformly dispersed in the gap
109
. Slight heating of the packaging substrate after dispensing of the underfill epoxy assists the flow. In some cases, the underfill epoxy flow is further assisted by vacuum, or, alternatively, by injection of the epoxy into the gap
109
.
After the epoxy
108
has bled through the gap
109
, a separate bead of epoxy
111
may also be dispensed and bonded around the perimeter of the chip
100
. Thereafter, the epoxy (both the underfill and perimeter bonding epoxy (also referred to as a “fillet”), if any) are cured by heating the substrate and chip to an appropriate curing temperature. In this manner the process produces a mechanically, as well as electrically, bonded semiconductor chip assembly, with the underfill material
108
allowing a redistribution of the stress at the connection between the chip
100
and the substrate
106
from the solder
104
joints only to the entire sub-chip area.
FIG. 1C
shows the chip
100
interconnected to the packaging substrate
106
electrically by solder
104
joints and mechanically by a cured layer of epoxy
108
in the gap
109
between the chip
100
and the solder mask
101
on the packaging substrate
106
.
Underfill materials typically have from about 6 to 8 components including an epoxy base and filler materials which are used to control the shrinkage, CTE and modulus of the cured underfill material. The filler in underfill materials increases the viscosity of the materials and thus detracts from its ability to easily flow (“wick”) and uniformly fill the gap
109
. This problem is exacerbated with decreasing semiconductor device sizes where ball pitch is decreasing to approximately 225 to 200 microns, raising the prospect of narrower gaps in conventional package designs, for example gaps decreased in size to between about 25 to 50 microns and to even less than 25 microns. These decreased gap sizes increase the difficulty of flip chip underfill processing. In particular, a smaller gap impedes the flow (“wicking”) of underfill between the chip and substrate and increases the likelyhood of entrapping voids within the underfill. Voids that bridge two solder balls (or bumps) can result in electrical shorting during subsequent processing of the package. Voids can also provide pathways for metal migration, which could result in electrical leakage or shorting in the package. These defects represent yield, quality or reliability problems
Beyer Weaver & Thomas LLP
LSI Logic Corporation
Nelms David
Nhu David
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