Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2011-08-23
2011-08-23
Lebentritt, Michael S (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S374000, C257S466000, C257SE21409, C257SE21424, C257SE21551, C257SE27006, C257SE29193, C257SE29226, C257SE29255
Reexamination Certificate
active
08004035
ABSTRACT:
A dual stress liner manufacturing method and device is described. Overlapping stress liner layers of opposite effect (e.g., tensile versus compression) may be deposited over portions of the device, and the uppermost overlapping layer may be polished down in a process that uses the bottom overlapping layer as a stopper. An insulating film may be deposited on the stress liner layers before the polishing, and another insulating film may be deposited above the first insulating film after the polishing. Contacts may be formed such that the contacts need only penetrate one stress liner layer to reach a transistor well or gate structure.
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2007-177644, JP Notification of Reasons for Rejection, Examiner's Notice date Jan. 25, 2010, mail date Feb. 2, 2010.
H.S. Yang, et al., “Dual Stress Liner for High Performance sub-45nm Gate Length SOI CMOS Manufacturing,” IEEE 2004; IEDM 04, pp. 1075-1077.
2007-177644, JP Notification of Reasons for Rejection, Examiner's Notice date May 23, 2011, mail date May 31, 2011.
Banner & Witcoff Ltd
Kabushiki Kaisha Toshiba
Lebentritt Michael S
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