Dual storage adapters utilizing clustered adapters...

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture

Reexamination Certificate

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Details

C710S052000, C710S072000, C711S141000, C711S112000, C711S118000

Reexamination Certificate

active

06728818

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to input/output (I/O) devices and, in particular, to I/O storage adapters. More particularly, the present invention relates to a dual storage adapter that utilizes I/O adapters that mirror write cache data and cache directory between them.
2. Description of the Related Art
Business use of computer systems has increased dramatically over the last half century. The use of the computer has also evolved and in today's business environment, more and more customers are becoming critically dependent on their information technology resources. As a result, they demand that these resources are always available. Any outage affecting their information technology resources has serious business implications including lost revenue and lost business. At the extreme, an extended system outage can cause a business to be permanently closed. Furthermore, the cost of one hour of system downtime can range from tens of thousands of dollars to several million dollars, depending on the nature of the business. Therefore, users require that their system services be continuously available, that is that the services be available 24 hours a day, 365 days a year. Technology that supports increased computer system availability has become critical to many businesses.
A key technology that enables systems to provide continuous availability is clustering. A cluster is a collection of one or more complete systems that operate together to provide a single, unified computing capability. The perspective from the end user is that the cluster operates as though it were a single system. Work can be distributed across multiple systems in the cluster and any single outage, planned or unplanned, in the cluster will not disrupt the services provided to the end user. The end user services can be relocated from system to system within the cluster in a relatively transparent fashion.
For computer systems, reliability is a measure of unexpected failures and availability is a measure of system downtime; the lower the downtime, the higher the availability. One can draw a relationship between reliability and availability, of course, because unexpected software and hardware failures are one cause of downtime. Thus, with all other factors being equal, a system with high reliability will also have high availability. To achieve continuous availability, more than just robust system availability is needed. Critical data and critical applications must also be resilient to outages and both must be accessible across the cluster even when the normal hosting system for the resource fails. A complete solution is achieved when the critical data and the critical applications are made to be resilient resources and are always available. Data resilience ensures that a copy of the data is always accessible to end users of the cluster while application resilience ensures that the services provided by the application are always accessible to end users of the cluster.
Input/output (I/O) storage adapters are interfaces between a computing system and a storage subsystem. In a high availability configuration, such as a cluster, redundant adapters are utilized to provide the necessary reliability, in the event that when a primary adapter fails, the backup adapter can takeover ensuring continued operation. When employing storage adapters that have resident write caches, the write cache data and directory information must be kept in synch, i.e., the cache data and directory information in the primary and backup adapters must mirror each other, to ensure a “flawless” takeover in the event of a failure in the primary adapter to maintain data resiliency.
Accordingly, what is needed in the art is a storage adapter with a resident write cache that can be clustered with another storage adapter with a resident write cache and still be ensured of data resiliency.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide an improved data processing system.
It is another object of the invention to provide a clustered dual storage adapter employing storage adapters that have resident write caches.
To achieve the foregoing objects, and in accordance with the invention as embodied and broadly described herein, an Input/Output (I/O) adapter for use with a second I/O adapter in a clustered configuration is disclosed. The I/O adapter includes a dedicated communication link that, in an advantageous embodiment, is a high-speed serial bus. The communication link provides for communication between the I/O adapter and the second I/O adapter. The I/O adapter also includes a message passing circuit, coupled to the dedicated communication link, that allows for transferring of data between the I/O adapter and the second I/O adapter. The message passing circuit, in an advantageous embodiment, includes a transmit buffer, a receive buffer, a transmit register that initiates the transfer of data stored in the transmit buffer to the second I/O adapter and a receive register that indicates the receipt of data from the second I/O adapter. The I/O adapter further includes a doorbell circuit, coupled to the message passing circuit, that generates interrupts to provide a low level communication between the I/O adapter and the second I/O adapter. The doorbell circuit includes, in an advantageous embodiment, a transmit doorbell register that permits the I/O adapter to set bits in the second I/O adapter's corresponding receive doorbell register, a receive doorbell register and a mask doorbell register that allows for the masking of incoming receive doorbell interrupts. A mirroring directory, coupled to the message passing circuit, is also included in the I/O adapter to provide for the mirroring of cache directory writes. In a related embodiment, both the transferring of data and the performing of a write operation by the message passing circuit between the I/O adapter and the second I/O adapter is a write operation with no required acknowledgment from the second I/O adapter.
The present invention discloses a novel hardware assisted mechanism for mirroring required data and directory information between two clustered storage adapters that support fast write cache utilizing a dedicated, independent physical hardware communication link. The present invention allows the utilization of a synchronous firmware model instead of an asynchronous model to accomplish write cache directory updates. Thus, the implemented firmware does not need to wait for an update to cache directory to complete. The direct memory access (DMA) firmware setup for each write operation is almost identical to the firmware setup for a non-clustered write operation with a minimal delay added to each host write operation when compared to a non-clustered storage adapters configuration. Furthermore, the data protection mechanisms provided by the present invention prevent the firmware in the failed adapter from inadvertently corrupting data in either its own adapter or the backup data.
The foregoing description has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject matter of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.


REFERENCES:
patent: 4530052 (1985-07-01), King et al.
patent: 5463736 (1995-10-01), Elko et al.
patent: 5765195 (1998-06-01), McDonald
patent: 6434681 (2002-08-01), Armangau
patent: 6530003 (2003-03-01), Bakke et al.
“Design and analysis of cache coherent multistage interconnection networks” by A.

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