Dual silicide semiconductor fabrication process

Details Dual silicide semiconductor fabrication process Dual silicide semiconductor fabrication process

2007-06-26

2007-06-26

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S586000, C438S303000, C438S508000

Reexamination Certificate

active

11213470

ABSTRACT:
A semiconductor fabrication process includes forming a gate stack overlying semiconductor substrate. Source/drain regions are formed in the substrate laterally aligned to the gate stack. A hard mask is formed overlying a gate electrode of the gate stack. A first silicide is then formed selectively over the source/drain regions. After removing the hard mask, a second silicide is selectively formed on the gate electrode. The first silicide and the second silicide are different. Forming the gate stack may include forming a gate dielectric on the semiconductor substrate and a polysilicon gate electrode on the gate dielectric. The gate electrode may have a line width of less than 40 nm. Forming the second silicide may include forming nickel silicide in upper portions of the gate electrode.

REFERENCES:
patent: 6376320 (2002-04-01), Yu
patent: 6391767 (2002-05-01), Huster et al.
patent: 6524939 (2003-02-01), Tseng
patent: 6528402 (2003-03-01), Tseng
patent: 6727539 (2004-04-01), Divakaruni et al.

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