Dual silicide process to reduce gate resistance

Details Dual silicide process to reduce gate resistance Dual silicide process to reduce gate resistance

2000-02-11

2002-05-21

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S655000

Reexamination Certificate

active

06391767

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of semiconductor device manufacturing, and more particularly, to the formation of low resistivity self-aligned silicide regions on the gate and source/drain junctions of a semiconductor device.
BACKGROUND ART
In the manufacture of integrated circuits, a commonly used practice is to form silicide on source/drain regions and on polysilicon gates. This practice has become increasingly important for very high-density devices where the feature size is reduced to a fraction of a micrometer. Silicide provides good ohmic contact, reduces the sheet resistivity of source/drain regions in polysilicon gates, increases the effective contact area, and provides an etch stop.
A common technique employed in the semiconductor manufacturing industry is self-aligned silicide (“salicide”) processing. Salicide processing involves the deposition of a metal that forms intermetallic with silicon (Si) but does not react with silicon oxide or silicon nitride. Common metals employed in salicide processing are titanium (Ti), cobalt (Co), and nickel (Ni). These common metals form low resistivity phases with silicon, such as TiSi
2
, CoSi
2
, NiSi. The metal is deposited with a uniform thickness across the entire semiconductor wafer. This is accomplished using, for example physical vapor deposition (PVD) from an ultra-pure sputtering target and a commercially available ultra-high vacuum (UHV), multi-chamber, DC magnetron sputtering system. Deposition is performed after both gate etch and source/drain junction formation. After deposition, the metal blankets the polysilicon gate electrode, the oxide spacers, oxide isolation, and the exposed source and drain electrodes. A cross-section of an exemplary semiconductor wafer during one stage of a salicide formation process in accordance with prior art techniques is depicted in FIG.
1
.
As shown in
FIG. 1
, silicon substrate
10
has been provided with source/drain junctions
12
,
14
and a polysilicon gate
16
. Oxide spacers
18
have been formed on the sides of the polysilicon gate
16
. Refractory metal layer
20
, comprising cobalt, for example, has been blanket deposited over the source/drain junctions
12
,
14
, polysilicon gate
16
, and the spacer
18
. The metal layer
20
also blankets oxide isolation regions
22
that isolate the devices from one another.
A first rapid thermal anneal (RTA) step is then performed at a temperature of between about 450°-700° C. for a short period of time in a nitrogen atmosphere. The nitrogen reacts with a metal to form a metal nitride at the surface of a metal, while the metal reacts with silicon and forms silicide in those regions where direct contact with the silicon. Hence, the reaction of the metal with the silicon forms a silicide
24
on the gate
16
and source/drain regions
12
,
14
, as depicted in FIG.
2
.
After the first rapid thermal anneal step, any metal that is unreacted is stripped away using a wet etch process that is selective to the silicide. A second, higher temperature rapid thermal anneal step, for example above 700° C., is applied to form a lower resistance silicide phase of the metal silicide. The resultant structure is depicted in
FIG. 3
in which the higher resistivity-phase metal silicide
24
has been transformed to the lowest resistivity phase metal silicide
26
. For example, when the metal is cobalt, the higher resistivity phase is CoSi and the lowest resistivity phase is CoSi
2
. When the polysilicon and diffusion patterns are both exposed to the metal, the silicide forms simultaneously over both regions. This method is considered to be a “salicide” method since the silicides formed over the polysilicon and single-crystal silicon are self-aligned to each other.
In cobalt silicide technologies, as in titanium silicide technologies, the silicon is consumed by the reaction to form the silicide. As the industry moves to shallower junctions to increase switching speed of the semiconductor devices, overly large silicon consumption results in insufficient distance between the bottom of the silicide and the bottom of the source/drain junctions, and therefore results in junction leakage. An example of this problem is depicted in prior art FIG.
3
. The cobalt silicide regions
26
are depicted as extending to the bottom of the source/drain junctions
12
,
14
so as to create junction leakage.
One of the important factors which determine the maximum speed at which a circuit can operate in CMOS technologies is the resistance of the gate. This is the reason that the top of the gate in CMOS technologies is typically converted to a silicide, such as is shown in FIG.
3
. The larger the silicide layer, the lower the resistance and the faster the semiconductor device will operate. However, the creation of too much silicide produces the problem of “bridging” between the gate silicide and the source/drain silicides.
BRIEF SUMMARY OF THE INVENTION
There is a need for a method of reducing the gate resistance in a semiconductor device that increases the amount of silicide on the gate without producing a bridging problem between the gate silicide and the source/drain silicides. Also, there is a need for a method of reducing the gate resistance of a semiconductor device without excessive consumption of silicon in the source/drain regions, thereby allowing the formation of ultra-shallow junctions.
These and other needs are met by the present invention which provides a method of reducing gate resistance in a semiconductor device comprising the steps of forming a silicide region only on a gate of a semiconductor device, and forming silicide on a source/drain of the semiconductor device and on the previously formed silicide region.
One of the advantages of the present invention is that the method produces a thicker silicide region only on the gate of the semiconductor device, while the silicide on the source/drain areas of the semiconductor device may remain a conventional thickness. This reduces the possibility of bridging and prevent excessive silicon consumption, while reducing the resistance at the gate.
The earlier stated needs are met by another embodiment of the present invention which provides a method of reducing gate resistance in the semiconductor device, comprising the steps of forming a gate and forming silicide to a first thickness on the gate while simultaneously preventing silicide formation on other portions of the semiconductor device. The thickness of the silicide on the gate is then increased to a second thickness and silicide is simultaneously formed on at least some of the other portions of the semiconductor device.
The formation of silicide on a gate to a first thickness, while simultaneously preventing silicide formation on other portions of the semiconductor device, permits tailoring of the gate resistance without excessive consumption of silicon in the source/drain areas and bridging between the gate and the source/drain silicide regions.
The foregoing and other features, aspects and advantages of the present invention will become more apparent in the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5084417 (1992-01-01), Joshi et al.
patent: 5352631 (1994-10-01), Sitaram et al.
patent: 5723893 (1998-03-01), Yu et al.
patent: 5856225 (1999-01-01), Lee et al.
patent: 5953616 (1999-09-01), Ahn
patent: 6037204 (2000-03-01), Chang et al.
patent: 6063681 (2000-05-01), Son
patent: 6180469 (2001-01-01), Pramanick et al.
patent: 6200871 (2001-03-01), Moslehi
patent: 6225176 (2001-05-01), Yu

Affiliated with

Also associated with

Rating

Dual silicide process to reduce gate resistance does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual silicide process to reduce gate resistance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual silicide process to reduce gate resistance will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2823163