Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
2001-10-09
2004-02-10
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C710S060000, C710S061000, C710S069000, C710S074000
Reexamination Certificate
active
06691186
ABSTRACT:
TECHNICAL FIELD
The present invention relates to peripheral storage devices and, more particularly, to hard drive disk control systems used in peripheral storage devices.
BACKGROUND OF THE INVENTION
Hard disk drives and other peripheral storage devices have become a standard feature in most computer systems. Such devices provide mass storage functionality for a host computer, and may include hard disk drives, CDROM drives, tape drives, optical disk memory devices, floppy disk drives, and the like. For example, hard disk drives include one or more magnetically coated platters used for storing program instructions, data, and other information used by the computer system. For example, as illustrated in prior art
FIG. 1
, one or more such platters may be configured in a stack
2
for rotation about a spindle platter
7
by a spindle or servo motor
3
. A space is provided between each platter to allow an arm
4
having a read/write head
5
to be positioned on each side of each platter such that information may be stored and retrieved.
The read/write heads
5
may be mounted onto one or more suspension arms
4
, whereby each of the read/write heads
5
may be positioned as desired. The suspension arms may be coupled together at a voice coil motor (VCM)
6
to form one unit or assembly that is positioned by the voice coil motor
6
. The voice coil motor
6
positions the suspension arms
4
so that an active read/write head
5
is properly positioned for reading or writing information. The read/write heads may thus be positioned between an inner diameter and an outer diameter of the platters in a controlled fashion to access data stored thereon.
Hard disk drives and other types of peripheral storage devices also include a variety of electronic control circuitry for processing data and for controlling its overall operation. For example, the circuitry may include a pre-amplifier (typically mounted on the suspension arm
4
local to the read/write head), a read channel circuit
8
, a motor control circuit
9
, a disk formatter circuit
10
, an error checking circuit
11
, and a variety of disk control circuitry to control the operation of the hard disk drive and to properly interface the hard disk drive system to a bus
13
in a host computer system (not shown). The disk drive may further comprise some form of buffer memory
14
to buffer or temporarily store information as it is processed from the host system to the storage media (platters)
1
and/or from the media
1
to the host system. In addition, the control circuitry may include instruction memory (e.g., ROM, EEPROM, FLASH, or the like) used for storing firmware instructions for execution by the controller processor, and execution memory (e.g., SRAM) used for storing temporary variables, intermediate results, and the like (scratchpad, not shown).
The disk control circuitry generally includes a processor (e.g., a DSP, microprocessor, microcontroller, or the like) for executing instructions stored in memory to control the operation and interface of the hard disk drive. Within this is circuitry, there exist a functional block of logic commonly known as a disk formatter
10
. This disk formatter
10
performs both data path and control path operations. Its primary duty is to receive timing information from its inputs and then control the sequence of read or write operations. In addition it controls the length, or amount, of read/write operations allowed on the media. Its inputs are typically a sub servo subsystem (the motor control circuit
9
), the error checking system
11
, the buffer manager
14
(which interfaces with the host computer via an interface (not shown)) and the read channel logic
8
which retrieves/stores the read/write data from/to the storage medium.
Hard disk drives and other peripheral storage devices perform write, read, and servo operations when storing and retrieving data. Generally, a write operation includes receiving data from the system bus
13
and storing the data on the platters. The data on the platters is typically organized into circumferential tracks
21
with the data grouped along the tracks
21
in sectors
20
, as illustrated in prior art FIG.
2
. Accordingly, in a write operation, the data is transferred to the disk
22
in sectors
20
. In a read operation, the appropriate sector
20
to be read is located and data that has been previously written thereto is read. The data is then provided to the host computer system via the system bus
13
.
Peripheral storage devices, such as disk drive products are desired for a variety of different applications, each having different performance requirements. As the performance in the host computers improve, there exists a demand for larger data storage systems, faster hard drive data retrieval times, greater accuracy in data retrieval and increased data retrieval efficiencies. This is due, in part, to the software designer's expectations and requirements for improved graphics, etc.
As the storage media capabilities increase, the various problems associated with these medias are amplified. One such problem is a phenomenon, called channel latencies, which can cause data retrieval delays and wasted data storage space due to inefficient media space utilization. Previously, this problem could be ignored since the wasted data storage space due to channel latencies was relatively small compared to data storage capacities. However, with the ever increasing data storage capacities and their subsequent data transfers present in today's present computers, these channel latencies are becoming a more significant issue.
It should be noted that past channel latencies could be measured in terms of byte times on the order of 10 byte times (a byte time refers to the number of periods transpired by the clock which synchronizes the interface between the disk formatter and the read channel). Due to the increasing complexities and functionality of the read channel circuitry, present latencies are on the order of 10 to 70 byte times and future latencies are expected to be on the order of 3000 or greater byte times. It is anticipated that future latencies will be measured in sector times (approximately 800 bytes), resulting in a greater amount of wasted media storage space. In other words, with increased scale of data retrieval operations, it becomes rather evident that a solution to media storage channel latencies is necessary.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its primary purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention utilizes a dual sequencer in the disk formatter of hard drive circuitry. By using two sequencers, the tasks of handling the control signal timing and the data transfer signals are isolated from one another. Using this approach, the disk formatter can accommodate channel latencies of virtually any size without a substantial loss in data storage efficiency.
The dual sequencer of the present invention employs one sequencer, called a channel sequencer, which is tied to the timing of the data media and controls the read gate signals and the write gate signals (the control path). A second sequencer, called a NRZ sequencer, dictates the timing of the data as it is presented on a data transfer bus, called a NRZ bus (the data path). In other words one sequencer signals the circuitry when data is to be written or read from the media (the read or write gate signals), the other sequencer verifies that the data to be transferred is indeed valid data. Since the sequencers operate independently of one another in terms of time, the system employing the dual sequencer architecture can accommodate a channel latency of any size, including multiple
Thomson Steven E.
Wilson Brian
Brady W. James
Farooq Mohammad O.
Gaffin Jeffrey
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
LandOfFree
Dual sequencer based disk formatter does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dual sequencer based disk formatter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual sequencer based disk formatter will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3348705