Dual salicidation process

Details Dual salicidation process Dual salicidation process

2002-01-22

2003-02-25

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S303000, C438S306000, C438S586000, C438S595000

Reexamination Certificate

active

06524939

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to an integrated circuit fabrication. In particular, the present invention relates to a dual salicidation process that can form a silicide gate conductor having a greater thickness than a silicide structure on a source/drain region.
2. Description of the Related Art
In integrated circuit fabrication, the gate conductor is commonly used as a channel region mask during the formation of the source and drain junctions. One of the disadvantages of using polysilicon as the gate conductor material, however, is that it has a significantly higher resistivity than metals, such as aluminum. The propagation delay of an integrated circuit employing a polysilicon gate conductor may thus be longer than desired. Consequently, the operational frequency that can be achieved by a circuit employing a polysilicon gate conductor is somewhat limited.
To reduce the contact resistance at the contact/junction and contact/gate conductor interfaces, self-aligned low resistivity structures are commonly placed between the ohmic contacts and the junctions/gate conductors. The presence of these so-called self-aligned suicides (i.e., salicides) upon the junctions and gate conductors ensures that contact is made to the entire junction and gate areas. Further, forming salicide upon a polysilicon gate conductor helps lower the sheet resistance of the gate conductor. Salicide formed upon polysilicon is generally referred to as polycide.
Transistor device dimensions have been continuously reduced to accommodate the high demand for faster, more complex integrated circuits. As such, the source and drain junction depths have been reduced. Unfortunately, a salicide may completely consume a relatively shallow junction and penetrate into the substrate underneath the junction, a phenomenon known as “junction spiking”. Junction spiking may undesirably cause the junction to exhibit large current leakage or become electrically shorted. Therefore, in order to prevent excessive consumption of shallow junctions during contact formation, the junction salicide can only be of limited thickness. Since the gate and junction salicides are formed at the same time, the gate salicide also has a limited thickness. However, it is desirable to form a relatively thick layer of salicide upon a gate conductor to lower the sheet resistance of the gate conductor. Accordingly, it would be of benefit to develop a salicidation process in which the junction salicides and the gate salicides have dissimilar thicknesses. That is, the salicidation process must no longer require concurrent formation of the junction salicides and the gate salicides.
U.S. Pat. No. 6,100,173 discloses a dual salicidation process as shown in
FIGS. 1A
to
1
I. As shown in
FIG. 1A
, a semiconductor substrate
10
comprises shallow trench isolation structures
12
arranged a spaced distance apart for isolating active areas, a gate dielectric
14
formed on the substrate
10
, and a polysilicon gate conductor
16
patterned on the gate dielectric
14
by using well-known lithography and etch techniques. The gate dielectric
14
is made of a material having a K value greater than approximately
4
. The gate conductor
16
is made by polysilicon.
Next, as shown in
FIG. 1B
, source-side/drain-side LDD areas
18
are formed by self-aligning an LDD implant to the opposed sidewall surfaces of gate conductor
16
. Next, as shown in
FIG. 1C
, a dielectric material is deposited on the substrate
10
and then an anisotropical etching process is performed on the dielectric material. As a result, the dielectric material is only retained laterally adjacent the sidewalls surfaces of the gate conductor
16
in the form of sidewall spacers
22
.
As shown in
FIG. 1D
, a S/D implant self-aligned to the outer lateral surfaces of the sidewall spacers
22
is then performed at a higher dose and energy than the LDD implant. In this manner, source and drain regions
24
are formed within substrate
10
a spaced distance from gate conductor
16
. As such, LDD areas
18
and source and drain regions
24
form graded junctions which increase in concentration in a lateral direction away from gate conductor
16
.
Thereafter, as shown in
FIG. 1E
, a first metal layer
26
is deposited across exposed surfaces of gate dielectric
14
, sidewall spacers
22
, and gate conductor
16
. The first metal layer
26
may be made of cobalt and titanium. The first metal layer
26
may be subjected to radiation
28
to cause the metal atoms of the first metal layer
26
to undergo cross-diffusion and reaction with silicon atoms within polysilicon gate conductor
16
. As a result, a majority of polysilicon gate conductor
24
may be converted into a silicide gate conductor
30
, as shown in FIG.
1
F. The excess refractory metal not consumed during this salicidation process is removed using a selective etch technique. The resulting silicide gate conductor
30
comprises TiSi
2
if Ti is used as the refractory metal and CoSi
2
if Co is used as the refractory metal.
Turning to
FIG. 1G
, the gate dielectric
14
may then be removed from source and drain regions
24
. Subsequent to exposing the source and drain regions
24
, a second layer of refractory metal
32
, e.g., titanium or cobalt, may then be deposited across the semiconductor topography, as shown in FIG.
1
H. The second layer of refractory metal
32
is substantially thinner than the first layer of refractory metal
26
. The topography may then be exposed to radiation
34
to heat the second layer of refractory metal
32
. As a result of being annealed, metal atoms within the second layer of refractory metal
32
may react within underlying Si atoms of substrate
10
. In this manner, silicide structures
36
comprising, e.g., TiSi
2
or CoSi
2
are formed upon the source and drain regions
36
, as shown in FIG.
1
I. Any non-reacted refractory metal may be selectively etched away.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a dual salicidation process to form a relatively thick layer of the silicide gate conductor to lower the sheet resistance of the gate conductor.
The other object of the present invention is to provide a dual salicidation process in which silicide structures on source/drain regions are formed prior to silicide gate conductor on the polysilicon gate conductor.
A dual salicidation process is used on a semiconductor substrate which has a gate dielectric, a polysilicon gate conductor patterned upon a predetermined area of the gate dielectric, a sacrificial layer patterned upon the polysilicon gate conductor, and LDD areas formed within the substrate at opposed sidewall of the polysilicon gate conductor. First, an insulator spacer on the sidewall of the polysilicon gate conductor and the sacrificial layer, and then the gate dielectric not covered by the insulator spacer is removed. Next, source/drain regions are formed within the substrate at the outer lateral surfaces of the insulator spacer. Thereafter, using salicidation process, silicide structures are formed upon the source/drain regions. After removing the sacrificial layer salicidation process is used again to convert the polysilicon gate conductor into a silicide gate conductor.
It is an advantage of the present invention that the two-step salicidation process ensures that excessive consumption of source/drain regions does not occur during the formation of silicide gate conductor. Also, it is desirable to form a relatively thick layer of the silicide gate conductor to lower the sheet resistance of the gate conductor. Accordingly, the silicide structures and the silicide gate conductor have dissimilar thicknesses.
This and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.


REFERENCES:
patent: 5322809 (1994-06-01), Moslehi
patent: 5656519 (1997-08-01), Mogami et a

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