Dual row selection using multiplexed tri-level decoder

Details Dual row selection using multiplexed tri-level decoder Dual row selection using multiplexed tri-level decoder

1994-09-30

1996-05-14

Westin, Edward P.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

326106, 326 10, 365200, 36523006, H03K 19082

Patent

active

055171389

ABSTRACT:
A method and circuitry for providing dual row selection using a multiplexed tri-level decoder is disclosed. For one embodiment, the multiplexed tri-level decoder is a 3:8 decoder, the major components of which are a buffer and 8 three input NAND circuits. The NAND circuits are peculiar in that the inputs are referenced to a VCC operational voltage supply, and the outputs are referenced to a VPX tri-level supply voltage. The output of each NAND circuit is used to select one row or word line. During preconditioning and post conditioning, the decoder is required to enable two adjacent rows: the row selected and the next row. The present design implements dual row selection by adding a pass transistor that connects the word line enable driver to the driver of the previous row within the VPX level circuitry. This is in contrast to the previous design approach of implementing dual row selection by using VCC level logic. The disclosed implementation eliminates gates in the speed path of the circuit. This reduces the delay through the circuit. The new generation of flash memory requires reduction in read access time compared to that of previous generations. The disclosed tri-level decoder eliminates gates in the critical speed path, directly reducing read access time for the memory array.

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