Dual read/write register file memory

Details Dual read/write register file memory Dual read/write register file memory

1988-12-19

1990-06-12

Popek, Joseph A.

Static information storage and retrieval

Addressing

Multiple port access

36518904, 36523002, G11C 700

Patent

active

049339095

ABSTRACT:
A dual port read/write register file memory includes means for performing a read/modify write cycle of operation within a single system cycle of operation. The register file memory is constructed from one to more (RAM) addressable multibit storage arrays organized to form a dual read port, single write port RAM. Additionally, the register file includes a plurality of clocked input registers arranged in pairs for storing command, address and data signals for two write ports. The different pairs of registers are connected as inputs to a first set of multiplexer circuits whose outputs connect to the write control signal, address and data inputs of the single write port. The single write port of the register file memory is enabled for writing twice during each cycle. This allows data clocked into the input registers during the previous cycle to be written sequentially into the register file storage locations. By writing data into the input registers instead of the register file memory in a previous cycle, the time required for writing is reduced to a minimum.

REFERENCES:
patent: 4287575 (1981-09-01), Eardley et al.
patent: 4610004 (1986-09-01), Moller et al.
patent: 4623990 (1986-11-01), Allen et al.
Wafer Scale Interconnections for GaAs Packaging-Applications to RISC Architecture, by J. F. McDonald, et al., Computer published by IEEE, 4/87, pp. 21-35.
Toward a GaAs Realization of a Production-System Machine, by T. F. Lehr, et al., Computer published by IEEE, 4/87, pp. 36-46.
Publication No. 08786, Rev. B, Amendment O, Issue Date 8/87, AM29C334 by Advanced Micro Devices, pp. 1-19.

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