Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-09-15
2002-07-30
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C327S404000
Reexamination Certificate
active
06426647
ABSTRACT:
BACKGROUND
A. Technical Field
The present invention relates generally to driver circuits for a logic circuit, and more specifically to a dual rail driver circuit for a logic circuit.
B. Background of the Invention
Large arrays of logic circuits, such as content addressable memory devices (CAMs) typically share a common set of inputs driven by a driver circuit. Conventional logic circuitry for driver circuits typically employs singe rail inputs, i.e. a single input signal that represents either a logical zero or a logical one. For example, referring now to
FIG. 1
, there is shown a prior art logic circuit employing a single rail driver circuit. The logic circuit
100
comprises a plurality of logic blocks
102
. Each logic block is coupled to a single rail driver circuit
104
and local inputs
106
. The driver circuit
104
provides a common input signal to each of the logic blocks
102
.
Referring now to
FIGS. 2A and 2B
, there are shown a prior art inverter and a prior art NAND gate respectively. Prior art inverter
200
A comprises a p-channel transistor
204
and an n-channel transistor
206
. The prior art inverter
200
A further comprises a single input
202
to both the p-channel transistor
204
and the n-channel transistor
206
. The prior art NAND gate
200
B comprises two p-channel transistors,
208
and
210
, and two n-channel transistors,
212
and
214
. The prior art NAND gate
200
B further comprises two inputs,
216
and
218
. Input
216
provides a common input signal to both the p-channel transistor
208
and the n-channel transistor
212
. Thus, the prior art inverter
200
A and the prior art NAND gate
200
B are each driven by a prior art single rail driver circuit (not shown) that provides a single input signal
202
,
216
to both p-channel and n-channel transistors.
When a single rail driver circuit is used to drive a very large logic circuit, the input signal from the driver circuit may move very slowly from the threshold voltage for activating an n-channel transistor, for example, to the threshold voltage for activating a p-channel transistor. In such instances, there is typically a long period of time when both the p-channel transistors and the n-channel transistors in the logic circuit are on. One disadvantage of this setup is that a very high DC current runs through the logic circuit during that period. This spike in DC current results in a large power dissipation which is undesirable.
Accordingly it is desirable to provide a system and method for a driver circuit that uses a dual rail input for providing a common input to a logic circuit. It is also desirable to provide a driver circuit that provides a separate input signal for p-channel transistors and for n-channel transistors. Additionally, it is also desirable to provide a system and method for a driver circuit that decreases the power consumed by the logic circuit.
SUMMARY OF THE INVENTION
The present invention overcomes the deficiencies and limitations of the prior art with a unique system and method for a dual rail driver circuit for a logic circuit. A logic circuit in accordance with one embodiment of the present invention comprises a dual rail drive circuit having a first rail and a second rail. The logic circuit further comprises a first input coupled to receive an input signal from the first rail of the dual rail driver circuit, and a second input coupled to receive an input signal from the second rail of the dual rail driver circuit. In one embodiment, the input signal from the first rail of the dual rail driver circuit can swing to a voltage level sufficient to turn on a p-channel transistor, and the input signal from the second rail of the dual rail driver circuit can swing to a voltage level sufficient to turn on an n-channel transistor. For example, for a 0.18 micron process the input signal from the first rail may have a voltage swing from VDD to VDD-400 MV, and the input signal from the second rail may a voltage swing from ground to 400 MV.
In one aspect, the dual rail driver circuit comprises two rails, a plus rail and a minus rail. The dual rail circuit driver further comprises a plus rail voltage reference for generating a voltage appropriate for activating an n-channel transistor, and a plus rail driver, coupled to receive a signal from the plus rail voltage reference, for driving the voltage onto the plus rail. The dual rail driver circuit also comprises a minus rail voltage reference for generating a voltage appropriate for activating a p-channel transistor, and a minus rail driver, coupled to receive a signal from the minus rail voltage reference, for driving the voltage onto the minus rail.
These and other features and advantages of the present invention may be better understood by considering the following detailed description of preferred embodiments of the invention. In the course of this description, reference will be frequently made to the attached drawings.
REFERENCES:
patent: 5021684 (1991-06-01), Ahuja et al.
Chang Daniel D.
Fast-Chip, Inc.
Fenwick & West LLP
Tokar Michael
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