Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2000-12-22
2003-04-22
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S086000, C327S077000, C365S189090
Reexamination Certificate
active
06552569
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is generally directed to an integrated circuit interface to a memory device and, more specifically, to an input interface for high-speed, high-power signals and low-speed, low-power signals in an integrated circuit interface to a memory device.
BACKGROUND OF THE INVENTION
In networking technology a “thin client” is a type of network appliance. A thin client has a minimal on-board operating system and functions by downloading applications from a remote server to run locally. Generally, a thin client has little storage capacity and frequently has no mass storage capability, such as a hard disk drive. For example, a thin client that is used with the Internet may be a television set top box that connects to the Internet. A thin client that is used with the Internet may sometimes be referred to as an “Internet appliance.” An example of an Internet appliance is Compaq Computer's IPAQ-1.
The term “network appliance” will be used to refer to a thin client, an Internet appliance, and other similar types of equipment. A network appliance has the advantage of being much cheaper than a personal computer. Network appliances generally have a small form factor and are very quiet because there is no need for a fan. A network appliance is connected to a keyboard, television set or display and a network, usually a cable network. Network appliances are also available in battery powered and line current powered versions. With line current powered versions there is little need for restricting the processor to a low power drain circuit as there is plenty of power available. A line current network appliance is able to use Stub Series Terminated Transceiver Logic (SSTL) to drive double data rate (DDR) range in the random access memory (RAM) on board the network appliance. An input device utilizing SSTL is relatively fast, but has a substantial power requirement. On the other hand, a battery powered network appliance requires a low power drain because the on board RAM operates in the single data rate (SDR) range. The memory input device is thus a low power device. It is preferable to use Low Voltage Transistor-Transistor Transistor Logic (LVTTL) to power the memory.
LVTTL is commonly used to define voltage levels recognizable by low power memory devices. For instance, a relatively high voltage may be recognized as a one (“1”) , while a relatively low voltage may be recognized as a zero (“0”). Input buffers or receivers in certain memory devices that receive these levels have to be able to recognize whether a voltage is intended to be a high or low voltage. LVTTL dictates that all voltages higher than a specified high input voltage are interpreted as a “high” voltage and all voltages lower than a specified low input voltage are interpreted as a “low” voltage.
Joint Electronic Devices Engineering Council (JEDEC) established an SSTL1 specification and later established an SSTL2 specification. In the SSTL2 specification, the legal voltage swings for direct current (DC) are from:
VIH
(high input voltage)=
V
REF+0.18 volts
VIL
(low input voltage) =
V
REF−0.18 volts.
In the SSTL2 specification, the legal voltage swings for alternating current (AC) are from:
VIH
(high input voltage)
V
REF−0.35 volts
VIL
(low input voltage)=
V
REF−0.35 volts.
The reason for the different voltages is that the alternating current is run at system speed (e.g., 200 MHz) and the additional swing in voltage gives better noise margins.
In prior art input circuits that operate using the SSTL2 specification the data signal only has to swing above or below VREF by four or five hundred millivolts. Therefore, any direct current leakage that occurs between transistors in the input circuit is not a concern. Direct current leakage occurs in the SSTL2 mode because the data signal does not swing from “rail to rail” (i.e., from a maximum voltage level equal to the positive supply voltage (VDD) to a minimum voltage level equal to the negative supply voltage (VSS)). In the LVTTL mode, however, the data signal is driven from “rail to rail” and direct current leakage is not desired.
There is a need in the art for a dual purpose input circuit that will provide an input interface for both SSTL2 signals and LVTTL signals, so that the input circuit can process either type of signal. There is also a need in the art for a dual purpose input circuit that will provide zero direct current leakage when the dual purpose input circuit is operating in the LVTTL mode. There is also a need in the art for a dual purpose input circuit to provide zero direct current leakage when data signal voltages are swinging from “rail to rail.” There is also a need in the art for a dual purpose input circuit that will minimize the number of components in the input circuit and still provide zero direct current leakage when the input circuit is operating in the LVTTL mode.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide a dual purpose input circuit that is capable of processing both SSTL2 signals and LVTTL signals.
It is an additional object of the present invention to provide a dual purpose low power input circuit that is capable of reducing direct current leakage to zero when the input circuit is operating in an LVTTL mode.
The present invention comprises a multiplexer that is capable of receiving SSTL2 signals and LVTTL signals.
The present invention also comprises a switch containing a NAND gate that is capable of preventing the SSTL2 data signal from causing direct current leakage within the input circuit of the present invention when the input circuit is operating in an LVTTL mode.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the concept and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.
REFERENCES:
patent: 5696456 (1997-12-01), Lee
patent: 5949252 (1999-09-01), Taguchi
patent: 6020761 (2000-02-01), Hwang et al.
patent: 6023175 (2000-02-01), Nunomiya et al.
patent: 6064226 (2000-05-01), Earl
patent: 6104216 (2000-08-01), Satoh
patent: 617252
Chang Daniel
Davis Munck, P.C.
National Semiconductor Corporation
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