Active solid-state devices (e.g. – transistors – solid-state diode – Incoherent light emitter structure – With heterojunction
Reexamination Certificate
2001-12-18
2004-07-27
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Incoherent light emitter structure
With heterojunction
C257S190000, C257S103000, C257S076000, C257S613000, C438S518000, C438S046000, C438S022000
Reexamination Certificate
active
06768135
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the growth of epitaxial films. The invention also relates to the growth of a buffer layer on a substrate and the growth of an epitaxial film on the buffer layer. The invention further relates to the epitaxial deposition of heterostructures by more than one growth technique. The invention still further relates to a two stage, or dual, process for growing gallium nitride and related materials epitaxial layers.
2. Background of the Related Art
Gallium nitride (GaN) and its related nitrides, including AlN, InN and alloys of these materials, are emerging as important technological material. For example, GaN is currently used in the manufacture of blue light emitting diodes, semiconductor lasers, and other opto-electronic devices. However, it is currently impossible to fabricate bulk GaN crystals of usable size as substrates in semiconductor manufacturing. Thus, GaN films are made by deposition on a non-native substrate material, typically sapphire (Al
2
O
3
). However, a large lattice mismatch and thermal mismatch exists between the Al
2
O
3
substrate and the GaN layer. As a result, the material has large dislocation densities, which limit the performance of devices fabricated from these films, and at the same time restricts the applications for such GaN structures.
According to a prior art method for growing higher-quality GaN films, a relatively thick layer of an intermediate material can first be grown on the substrate as a buffer layer, and the GaN layer can then be grown on the buffer layer. Defects in GaN layers grown directly on sapphire substrates are due to major differences in inter-atomic spacing (lattice constant) and coefficient of thermal expansion (CTE) between the substrate and GaN. Therefore, if the buffer layer has a lattice constant and CTE closer to those of GaN, the GaN (top) layer will have fewer defects, and will be of higher quality. High quality GaN layers are necessary for electronic and opto-electronic devices. A material which meets the desired lattice constant and CTE criteria is aluminum nitride (AlN).
Prior art methods of fabricating heterostructures, having a GaN layer on a buffer layer, have used the same growth technique for both layers. For example, both semiconductors (the AlN buffer layer and the GaN layer) can be grown by metal-organic chemical vapor deposition (MOCVD). In this technique, ammonia gas (NH
3
) is reacted with a metallo-organic compound containing aluminum or gallium, such as trimethyl aluminum (TMA), triethyl aluminum (TEA), trimethyl gallium (TMG), or triethyl gallium (TEG). The reaction occurs at high temperatures in the vicinity of a substrate, and a solid product (GaN or AlN) is deposited on the substrate. However, this technique is not only expensive, but also slow. In particular, the metallo-organic source materials are costly, and they can only be delivered to the substrate for reaction at low rates.
A currently favored prior art technique for the growth of relatively thick layers, e.g., of GaN, is HVPE. In this process, growth proceeds due to the high-temperature vapor-phase reaction between gallium mono-chloride (GaCl) and ammonia. The ammonia is supplied from a standard gas source, while the GaCl is produced by passing hydrogen chloride (HCl) gas over a liquid gallium (Ga) supply. Using this method, GaN can be grown relatively quickly and inexpensively. Further, GaN grown at a fast rate may produce layers with less defect densities.
However, due to difficulties involved in providing a supply of aluminum chloride (AlCl), HVPE cannot be used for the efficient growth of an AlN buffer layer. (For example, when HCl is passed over Al metal, the AlCl that is formed immediately solidifies, and is not carried towards the substrate.) Consequently, AlN layers must be grown by techniques other than HVPE, such as MOCVD.
SUMMARY OF THE INVENTION
The above delineated disadvantages associated with prior art methods for deposition of AlN/GaN heterostructures are addressed by the present invention, in which a buffer layer (e.g., AlN) and an epitaxial layer (e.g., GaN) are grown using different techniques, as will be described fully hereinbelow.
In view of the above, it is an object of the present invention to provide a semiconductor heterostructure and method of making the same.
One feature of the invention is that it provides a two-stage process for fabricating a semiconductor heterostructure.
Another feature of the invention is that it provides a semiconductor heterostructure prepared by growing an epitaxial nitride layer on a buffer layer, the buffer layer deposited by a technique other than HVPE.
Another feature of the invention is that it provides a method of growing a semiconductor heterostructure, wherein a buffer layer is first grown on a substrate by metallo-organic chemical vapor deposition, and an epitaxial layer is subsequently grown on the buffer layer by hydride vapor-phase epitaxy.
Another feature of the invention is that it provides an epitaxial nitride layer formed on a substrate formed by MOCVD.
One advantage of the invention is that it provides a method for fabricating a semiconductor heterostructure by two different deposition processes, wherein each process is optimized for the material to be deposited.
Another advantage of the invention is that it provides an epitaxial layer formed by HVPE on a buffer layer formed by MOCVD.
Another advantage of the invention is that it provides an efficient method for forming an epitaxial nitride layer suitable for electronic and opto-electronic devices.
These and other objects, advantages and features are accomplished by the provision of a method of making a semiconductor heterostructure, including the steps of: a) providing a substrate; b) forming a buffer layer on the substrate to form a buffer-layered substrate; c) forming a cap layer on the buffer layer; and d) forming an epitaxial layer on the cap layer, wherein the buffer layer is formed by MOCVD, MBE or other suitable CVD techniques, and the epitaxial layer is formed by HVPE or other suitable techniques.
These and other objects, advantages and features are accomplished by the provision of a semiconductor heterostructure, including: a buffer layer, said buffer layer formed by MOCVD; and an epitaxial layer disposed on said buffer layer, said epitaxial layer formed by HVPE.
These and other objects, advantages and features are accomplished by the provision of an epitaxial layer prepared according to a method including the following steps: a) forming a buffer layer on a substrate by MOCVD, MBE, sputtering or other suitable CVD techniques; b) forming a cap layer on the buffer layer; and c) forming an epitaxial layer on the cap layer by hydride vapor-phase epitaxy.
These and other objects, advantages and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
REFERENCES:
patent: 4404265 (1983-09-01), Manasevit
patent: 4533410 (1985-08-01), Ogura et al.
patent: 4855249 (1989-08-01), Akasaki
patent: 4988640 (1991-01-01), Bohling et al.
patent: 5227328 (1993-07-01), Khan et al.
patent: 5290393 (1994-03-01), Nakamura
patent: 5468678 (1995-11-01), Nakamura
patent: 5587014 (1996-12-01), Iyechika et al.
patent: 5729029 (1998-03-01), Rudaz
patent: 5744375 (1998-04-01), Kao et al.
patent: 5770887 (1998-06-01), Tadatomo et al.
patent: 5810925 (1998-09-01), Tadatomo et al.
patent: 5814239 (1998-09-01), Kaneko et al.
patent: 5875052 (1999-02-01), Shmagin et al.
patent: 5891790 (1999-04-01), Keller et al.
patent: 5993542 (1999-11-01), Yanashima et al.
patent: 6023077 (2000-02-01), Iyechika et al.
patent: 6064078 (2000-05-01), Northrup et al.
patent: 6110531 (2000-08-01), Paz de Araujo et al.
patent: 6156581 (2000-12-01), Vaudo
patent: 6177292 (2001-01-01), Hon
Miller David J.
Solomon Glenn S.
Ueda Tetsuzo
CBL Technologies, Inc.
Isenberg Joshua D.
JDI Patent
Yevsikov Victor V
LandOfFree
Dual process semiconductor heterostructures does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dual process semiconductor heterostructures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual process semiconductor heterostructures will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3253030