Electronic digital logic circuitry – Interface – Supply voltage level shifting
Patent
1998-02-23
2000-01-25
Tokar, Michael
Electronic digital logic circuitry
Interface
Supply voltage level shifting
326 83, 326 68, 326121, H03K 190175
Patent
active
060182520
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a dual-power type integrated circuit for converting voltage amplitude of a logic signal to be output, and particularly to a dual-power type integrated circuit formed by use of an N-type semiconductor substrate.
BACKGROUND ART
In the field of computer equipment, there is widely used an integrated circuit which processes a logic signal with voltage amplitude of 3.3 V. In recent years, there is developed an integrated circuit in which the logic signal is processed with voltage amplitude of below 3.3 V for the purpose of saving power. A dual-power type integrated circuit generates a logic signal with voltage amplitude of 3.3 V, and converts the voltage amplitude of the logic signal from 3.3 V to 2.5 V to be output.
The conventional dual-power type integrated circuit is formed by use of a P-type semiconductor substrate 10 as shown in FIG. 5. In this integrated circuit, a logic processing section 1 generates a logic signal with voltage amplitude of 3.3 V, and a voltage amplitude converting section 2 converts voltage amplitude of the logic signal supplied from the logic processing section 1 from 3.3 V to 2.5 V to be output. The logic processing section 1 is a CMOS inverter in which a P-channel MOS transistor TP formed in an N-type well NW1 and an N-channel MOS transistor TN formed in a semiconductor substrate 10 are connected to operate at a power voltage of 3.3 V. The voltage amplitude converting section 2 is a CMOS inverter in which a P-channel MOS transistor TP formed in an N-type well NW2 and an N-channel MOS transistor TN formed in the semiconductor substrate 10 are connected to operate at a power voltage of 2.5 V. The semiconductor substrate 10 is connected to a ground terminal GND (=0 V) through a P.sup.+ -type contact region C0. The well NW1 is connected to a power source terminal VCC (=3.3 V) through an N.sup.+ -type contact region C1. The well NW2 is connected to a power source terminal VCCQ (=2.5 V) through an N.sup.+ -type contact region C2.
In a case where an N-type semiconductor substrate 20 is used to form the dual-power type integrated circuit as shown in FIG. 6, the P-channel MOS transistor TP is formed in the N-type semiconductor substrate 20, the N-channel MOS transistor TN is formed in a P-type well PW, and the semiconductor substrate 20 is connected to the power source terminal VCCQ (=2.5 V) through the N.sup.+ -type contact region C2, so that the voltage amplitude converting section 2 can be made equivalent to that shown in FIG. 5.
However, if the stable operation of the logic processing section 1 has priority over other operations, the semiconductor substrate 20 must be connected to the power source terminal VCC (=3.3 V) through the N.sup.+ -type contact region C1, and the N.sup.+ -type contact region C2 is electrically separated from the power source terminal VCCQ.
This separation makes it difficult to ensure a reverse-bias of a diode D which is formed of a PN junction between the P.sup.+ -type source region of the P-channel MOS transistor TP and the N-type semiconductor substrate 20 as shown in FIG. 2. In other words, to reverse-bias the diode D, the potential of the power source terminal VCC (=3.3 V) must rise prior to the potential of the power source terminal VCCQ (=2.5 V) or simultaneously with the potential of VCCQ. If the potential of the power source terminal VCC rises later than that of the power source terminal VCCQ, the diode D is temporarily forward-biased. As a result, an excessive forward current flows in the diode D and current paths connecting the diode D with the power source terminals VCC and VCCQ. The current also flows in current paths connecting the power source terminals VCC and VCCQ with an external power supply device on a circuit board. This exerts unfavorable influence onto the other integrated circuits mounted on the circuit board. Or, there is possibility that element destruction will occur by the excessive forward current flowing in the diode D.
An object of the present invention is to provide a dual-power ty
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patent: 5559464 (1996-09-01), Orii et al.
patent: 5789942 (1998-08-01), Mizuno
patent: 5900741 (1999-05-01), Roohparvar
Chang Daniel D.
NKK Corporation
Tokar Michael
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