Dual port video memory system having pulse triggered dual column

Details Dual port video memory system having pulse triggered dual column Dual port video memory system having pulse triggered dual column

1992-04-28

1993-10-19

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

365220, 36523005, 365239, 365240, G11C 700

Patent

active

052552209

ABSTRACT:
Read column conductors and write column conductors of a memory array are addressed by respective triggerable sequential pulse generators which, upon receiving respective trigger pulses, provide respective read and write address pulses to respective column conductors of the array. Data to be stored is written in parallel to cells of the memory a column at a time at a rate determined by the write sequential pulse generator and is recovered a column at a time at a rate determined by the read sequential pulse generator. Advantageously, (1) the ratio of the read and write rates may be selected to provide time compression, time expansion or constant delay of video data; (2) additionally data may be written and read concurrently without bus contention and (3) addressing is simplified by a timed application of trigger pulses to the pulse generators whereby there is no need for application to the memory of binary addressing data.

REFERENCES:
patent: 3763480 (1973-10-01), Weimer
patent: 4321695 (1982-03-01), Redwine et al.
patent: 4541076 (1985-09-01), Bowers et al.
patent: 4821226 (1989-04-01), Christopher et al.
patent: 4945518 (1990-07-01), Muramatsu et al.
Motorola Memories, Series E, Second Printing, 1988, Motorola Semiconductor Technical Data, MCM68HC34, pp. 5--3-5--10.

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