Dual port static memory with one cycle read-modify-write

Details Dual port static memory with one cycle read-modify-write Dual port static memory with one cycle read-modify-write

1992-08-19

1993-08-10

Dixon, Joseph L.

Static information storage and retrieval

Systems using particular element

Flip-flop

365174, 365190, 365203, 36523005, G11C 700, G11C 1100, G11C 1134, G11C 800

Patent

active

052355438

ABSTRACT:
A dual port static memory cell with one cycle read-modify-write operation. The static memory cell includes a write line for receiving new data to be written into the static memory cell, switching means for coupling the new data into the static memory cell, and an extended word line generator for generating an extended word line signal. The extended word line signal controls the switching means. During the active state of the extended word line signal, the switching means is enabled to couple new data into the static memory cell while precharge is placed on a bit line coupled to the static memory cell, without disturbing the precharge. The extended word line signal goes active in response to an active state of the word line signal and remains active even after the word line signal goes inactive. The extended word line signal returns to an inactive state prior to the beginning of a new memory cycle. The inactive state of the extended word line signal decouples the new data from the switching means. During a read-modify-write operation precharge on the bit lines after the read operation is undisturbed when writing occurs into the cell from the write lines. In the dual port memory a conflict determining circuit is used to provide a predetermined state to the cell when simultaneous access is sought for writing to the cells with conflicting data.

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