Dual port SRAM cell

Details Dual port SRAM cell Dual port SRAM cell

2006-10-03

2006-10-03

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Multiple port access

C365S154000, C365S156000, C365S205000

Reexamination Certificate

active

07116605

ABSTRACT:
The present invention provides a SRAM that is capable of performing a writing and reading operations simultaneously without collision while reducing size of cell, by providing a dual port SRAM cell. For this, the dual port SRAM cell, including: a writing section having a first transistor for inputting a data input signal from a bit line in response to a control signal from a word line; a data storage section having three transistors for storing the data input signal from the outside through the writing section; and a reading section having two transistors for reading the data input signal stored in the data storage section in response to control signal from a common line.

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patent: 5325338 (1994-06-01), Runaldue et al.
patent: 5561638 (1996-10-01), Gibson et al.
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patent: 6222777 (2001-04-01), Khieu
patent: 6598198 (2003-07-01), Furuta et al.

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