Dual port shared memory system including semaphores for high pri

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

711148, 711149, 711150, 711151, 711152, G06F 1300

Patent

active

061227137

ABSTRACT:
A system and method for controlling access to a dual port shared memory in a system comprising a host computer system and a communication device comprised in or coupled to the host computer system. The communication device includes the shared memory and also includes a local processor which executes a communication application. The shared memory is accessible by both the host computer and the local processor on the communication device. The board or local processor has deterministic and/or real time requirements and is thus the high priority requester, while the host CPU or host computer is the low priority requester. If the high priority side (board) gains the semaphore first, then accesses by the low priority side (host computer) are blocked until the write is finished. In the case of a host read/board write, if the low priority side gains the semaphore first, then the high priority side write can pre-empt the low priority side read. In this case, to avoid data integrity issues, the low priority side is required to verify that it still owns the semaphore after it finishes its read access, and the access fails if the low priority side does not own the semaphore at the time the read is completed. In the case of a host write/board read, if the low priority side gains the semaphore first, then the high priority side does not simply pre-empt to the low priority side as in the high to low data transfer direction. Rather, in this instance, when the high priority side determines that the low priority side owns the semaphore, the high priority side reads previously read data from a local buffer.

REFERENCES:
patent: 4964040 (1990-10-01), Wilcox
patent: 5434975 (1995-07-01), Allen
patent: 5623670 (1997-04-01), Bohannon et al.
patent: 5842015 (1998-11-01), Cunniff et al.
patent: 5872980 (1999-02-01), Derrick et al.
"5136-DN DeviceNet Scanner Module," Reference Guide, Version 2.1, S-S Technologies Inc., Jan. 24, 1997, 62 pages.
"Synchronizing shared objects", Kiser, M.; Zogg, A. Applications of Object-Oriented Programming, IEE Colloquium on, 1989, Page(s):4/1-4/5.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Dual port shared memory system including semaphores for high pri does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual port shared memory system including semaphores for high pri, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual port shared memory system including semaphores for high pri will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1084017

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.