Dual port semiconductor memory device with high speed data trans

Details Dual port semiconductor memory device with high speed data trans Dual port semiconductor memory device with high speed data trans

1991-11-18

1994-07-05

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Serial read/write

36518905, 365220, 36523005, G11C 700, G11C 800

Patent

active

053273869

ABSTRACT:
A dual port memory is disclosed capable of serial data reading and writing between a memory array including a memory cell formed by one MOS transistor and one capacitor and a single data input/output line. A flipflop and a sense amplifier are provided corresponding to each memory cell column of the memory array. Each flipflop includes a first inverter having a large drive capability and a second inverter having a small drive capability, connected to the input end and the output end of each other. The input end of the first inverter is connected to the corresponding sense amplifier via a single MOS transistor. The output ends of the firs and second inverters are connected to the data input/output line via first and second MOS transistors, respectively. At the time of data reading from the memory array to the data input/output line, the single MOS transistor and the first MOS transistor conduct. At the time of data writing from the data input/output line to the memory array, the single MOS transistor and the second MOS transistor conduct. Accordingly, the first inverter implements a transfer path of the stored data of the memory array from the sense amplifier to the data input/output line. The second inverter implements a transfer path of an external data from the data input/output line to the sense amplifier.

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